Patents by Inventor Wei Wen

Wei Wen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240151900
    Abstract: A method for manufacturing a semiconductor device includes: forming a first waveguide structure and a second waveguide structure on a substrate in which the first waveguide structure and the second waveguide structure is spaced apart from each other by a recess; conformally forming an un-doped dielectric layer to cover the first and second waveguide structures and to form a gap between two corresponding portions of the un-doped dielectric layer laterally covering the first waveguide structure and the second waveguide structure, respectively; and forming a doped filling layer to fill the gap.
    Type: Application
    Filed: February 22, 2023
    Publication date: May 9, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Li LO, Huan-Chieh CHEN, Yao-Wen CHANG, Chih-Ming CHEN
  • Publication number: 20240155106
    Abstract: Methods and devices are provided for decoding a video block in GPM. The method includes: partitioning the video block into first and second geometric partitions; receiving a first GPM with a motion vector refinement (GPM-MVR) enable flag for the first geometric partition and receiving a second GPM-MVR enable flag for the second geometric partition; receiving a joint template matching (TM) enable flag for the first and second geometric partition that jointly indicates whether a uni-directional motion of the first partition is refined by TM and whether a uni-directional motion of the second partition is refined by the TM; receiving a first merge GPM index for the first geometric partition and a second merge GPM index for the second geometric partition; constructing a uni-directional MV candidate list of the GPM; and generating a uni-directional MV for the first geometric partition and a uni-directional MV for the second geometric partition.
    Type: Application
    Filed: December 20, 2023
    Publication date: May 9, 2024
    Applicant: BEIJING DAJIA INTERNET INFORMATION TECHNOLOGY CO., LTD.
    Inventors: Xiaoyu XIU, Wei CHEN, Che-Wei KUO, Hong-Jheng JHU, Ning YAN, Yi-Wen CHEN, Xianglin WANG, Bing YU
  • Patent number: 11978947
    Abstract: A Rugged portable device comprises: a base, a cover pivotally connected to the base, a first antenna unit, a second antenna unit, and a control unit. The first antenna unit and the second antenna unit are respectively disposed at an edge of the cover and an edge of the base, and the first antenna unit and the second antenna unit respectively have a near-field antenna and a far-field antenna. When the cover pivots relative to the base and is close to the base, the near-field antenna disposed at the cover and the near-field antenna disposed at the base generate a near-field communication (NFC) sensing signal and the near-field communication sensing signal is transmitted to the control unit. Therefore, the control unit sets up one of functions in the rugged portable device. For instance, the control unit switches off and/or switches on the far-field antenna or a peripheral unit (a keyboard or a camera).
    Type: Grant
    Filed: November 29, 2021
    Date of Patent: May 7, 2024
    Assignee: Winmate Inc.
    Inventors: Ku-Ching Lu, Wei-Wen Yang, Hsin-Chin Wang, Chun-Yu Huang
  • Patent number: 11976229
    Abstract: The present invention belongs to the technical field of liquid crystal materials, and in particular relates to a negative liquid crystal composition and a liquid crystal display element or liquid crystal display containing the liquid crystal composition. The present invention discloses a negative dielectric nematic liquid crystal composition, comprising a compound represented by Formula I, one or more compounds represented by Formula II, and one or more compounds represented by Formula III. The liquid crystal composition has a relatively low rotational viscosity (?1), a high clearing point (Cp), a good solubility and a high stability to heat and light (VHR) on the basis of maintaining an appropriate optical anisotropy (?n), and can be used for developing a liquid crystal display element or liquid crystal display with a low cell thickness, a wide temperature for display, and a fast response.
    Type: Grant
    Filed: August 25, 2020
    Date of Patent: May 7, 2024
    Assignee: Shijiazhuang Chengzhi Yonghua Display Material Co., ltd.
    Inventors: Wei Zhang, Qing Cui, Gang Wen, Sumin Kang
  • Publication number: 20240143880
    Abstract: A method includes determining a first timing of a transition sequence of a signal on a first path of an integrated circuit (IC) design, the first timing being based on an IC design signoff voltage, determining a second timing of the transition sequence of the signal on the first path, the second timing being based on the signoff voltage and a first voltage drop along the first path, calculating a first path derating factor based on a timing gap between the first and second timings of the transition sequence, and using the first path derating factor to evaluate the IC design.
    Type: Application
    Filed: January 27, 2023
    Publication date: May 2, 2024
    Inventors: Yu-Wen LIN, Bogdan TUTUIANU, Florentin DARTU, Wei-Chih HSIEH, Osamu TAKAHASHI
  • Publication number: 20240146945
    Abstract: Provided is a method for video decoding including: receiving a control variable enabling adaptive switch between motion vector refinement (MVR) offset sets; receiving an indication variable enabling adaptive switch between codeword tables that binarize offset magnitudes in the MVR offset sets under the coding level; partitioning the video block into a first and a second geometric partition; selecting an MVR offset set based on the control variable; receiving syntax elements to determine a first and second MVR offsets applied to the first and second geometric partitions from the selected MVR offset set; obtaining a first and second MVs from a candidate list for the first and the second geometric partition; calculating a first and second refined MVs based on the first and second MVs and the first and second MVR offsets; and obtaining prediction samples based on the first and second refined MVs.
    Type: Application
    Filed: December 14, 2023
    Publication date: May 2, 2024
    Applicant: BEIJING DAJIA INTERNET INFORMATION TECHNOLOGY CO., LTD.
    Inventors: Xiaoyu XIU, Wei CHEN, Che-Wei KUO, Hong-Jheng ZHU, Ning YAN, Yi-wen CHEN, Xianglin WANG, Bing YU
  • Publication number: 20240143455
    Abstract: A virtual machine backup method, performed by a first host, includes: capturing a request to write data from a virtual machine to a hard disk image file, wherein the request includes written data and input and output location information, copying the written data to a temporary storage area, calculating a first key of the written data, storing the first key, the input and output location information into a first resource location structure, pausing an operation of the virtual machine and generating a second resource location structure according to the first resource location structure, the first key and a second key, and outputting a backup data set to a second host according to the second resource location structure, wherein the backup data set includes the second resource location structure and only one of existing data and the written data when the first key and the second key are the same.
    Type: Application
    Filed: May 15, 2023
    Publication date: May 2, 2024
    Applicant: INSTITUTE FOR INFORMATION INDUSTRY
    Inventors: Lee Chung CHEN, Li Hao CHIANG, Gin CHI, Wei Jie HSU, Jiann Wen WANG, Wen Dwo HWANG
  • Publication number: 20240145435
    Abstract: Some implementations described herein include systems and techniques for fabricating a multi-dimension through silicon via structure in a three-dimensional integrated circuit device. The multi-dimension through silicon via structure includes a first columnar structure having a first width and a second columnar structure including a second width that is greater relative to the first width. The first columnar structure may include a low electrical capacitance and be configured for electrical signaling within the three-dimensional integrated circuit device. The second columnar structure may be configured to provide power to integrated circuitry of the three-dimensional integrated circuit device and also be configured to conduct heat through the three-dimensional integrated circuit device for thermal management of the three-dimensional integrated circuit device. Additionally, a pattern including the second columnar structure may be used for alignment purposes.
    Type: Application
    Filed: April 26, 2023
    Publication date: May 2, 2024
    Inventors: Ke-Gang WEN, Tsung-Chieh HSIAO, Liang-Wei WANG, Dian-Hau CHEN
  • Publication number: 20240145327
    Abstract: A semiconductor device includes a substrate, an interconnect structure, and conductive vias. The substrate has a first side, a second side and a sidewall connecting the first side and the second side, wherein the sidewall includes a first planar sidewall of a first portion of the substrate, a second planar sidewall of a second portion of the substrate and a curved sidewall of a third portion of the substrate, where the first planar sidewall is connected to the second planar sidewall through the curved sidewall. The interconnect structure is located on the first side of the substrate, where a sidewall of the interconnect structure is offset from the second planar sidewall. The conductive vias are located on the interconnect structure, where the interconnect structure is located between the conductive vias and the substrate.
    Type: Application
    Filed: December 27, 2023
    Publication date: May 2, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chang-Jung Hsueh, Cheng-Nan Lin, Wan-Yu Chiang, Wei-Hung Lin, Ching-Wen Hsiao, Ming-Da Cheng
  • Publication number: 20240141004
    Abstract: Diagnosis, treatment and prophylaxis of diseases and conditions associated with smooth muscle cell (SMC) dysfunction are provided through the inhibition or IL-11-mediated signalling.
    Type: Application
    Filed: August 31, 2023
    Publication date: May 2, 2024
    Applicants: Singapore Health Services PTE LTD., National University of Singapore
    Inventors: Stuart Alexander Cook, Sebastian Schaefer, Wei Wen Lim, Benjamin Wei Ming Ng
  • Patent number: 11971859
    Abstract: Techniques are provided for implementing a defragmentation process during a merge operation performed by a re-compaction process upon a log structured merge tree. The log structured merge tree is used to store keys of key-value pairs within a key-value store. As the log structured merge tree fills with keys over time, the re-compaction process is performed to merge keys down to lower levels of the log structured merge tree to re-compact the keys. Re-compaction can result in fragmentation because there is a lack of spatial locality of where the re-compaction operations re-writes the keys within storage. Fragmentation increases read and write amplification when accessing the keys stored in different locations within the storage. Accordingly, the defragmentation process is performed during a last merge operation of the re-compaction process in order to store keys together within the storage, thus reducing read and write amplification when accessing the keys.
    Type: Grant
    Filed: April 28, 2022
    Date of Patent: April 30, 2024
    Assignee: NetApp, Inc.
    Inventors: Anil Paul Thoppil, Wei Sun, Meera Odugoudar, Szu-Wen Kuo, Santhosh Selvaraj
  • Patent number: 11972975
    Abstract: A method of forming a semiconductor device structure is provided. The method includes forming a masking structure with first openings over a semiconductor substrate and correspondingly forming metal layers in the first openings. The method also includes recessing the masking structure to form second openings between the metal layers and forming a sacrificial layer surrounded by a first liner in each of the second openings. In addition, after forming a second liner over the sacrificial layer in each of the second openings, the method includes removing the sacrificial layer in each of the second openings to form a plurality of air gaps therefrom.
    Type: Grant
    Filed: June 24, 2021
    Date of Patent: April 30, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsi-Wen Tien, Wei-Hao Liao, Yu-Teng Dai, Hsin-Chieh Yao, Chih-Wei Lu, Chung-Ju Lee, Shau-Lin Shue
  • Publication number: 20240131612
    Abstract: Disclosed are a special tooling and method for electron beam welding of a cavity body and a beam tube of a superconducting niobium cavity. The special tooling includes a first clamping device for fixing a flange and a second clamping device for fixing a semi-cavity body, wherein the first clamping device and the second clamping device are fixedly connected. A pressing ring of the first clamping device is disposed around a beam tube of a superconducting niobium cavity and cooperates with a base plate to clamp and fix the flange. The second clamping device includes clamping arms evenly distributed along a circumference of the semi-cavity body, and each clamping arm includes a second pressing plate axially disposed along the beam tube and a pressing block that is disposed on an end portion of the second pressing plate and fixes an edge of the semi-cavity body.
    Type: Application
    Filed: October 18, 2023
    Publication date: April 25, 2024
    Inventors: Jianguo Ma, Wei Wen, Zhihong Liu, Jia Tao, Zhenfei Liu, Liming Peng, Nian Liu, Jiefeng Wu
  • Publication number: 20240136310
    Abstract: Semiconductor devices including one or more interfacing segments patterned within an outer protective layer and associated systems and methods are disclosed herein. The one or more interfacing segments may provide attachment interfaces/surfaces for connection pads. The one or more interfacing segments or a portion thereof may remain uncovered or exposed and provide warpage control for the corresponding semiconductor device.
    Type: Application
    Filed: January 3, 2024
    Publication date: April 25, 2024
    Inventors: Wei Zhou, Chien Wen Huang
  • Publication number: 20240135745
    Abstract: An electronic device has a narrow viewing angle state and a wide viewing angle state, and includes a panel and a light source providing a light passing through the panel. In the narrow viewing angle state, the light has a first relative light intensity and a second relative light intensity. The first relative light intensity is the strongest light intensity, the second relative light intensity is 50% of the strongest light intensity, the first relative light intensity corresponds to an angle of 0°, the second relative light intensity corresponds to a half-value angle, and the half-value angle is between ?15° and 15°. In the narrow angle state, a third relative light intensity at each angle between 20° and 60° or each angle between ?20° and ?60° is lower than 20% of the strongest light intensity.
    Type: Application
    Filed: January 3, 2024
    Publication date: April 25, 2024
    Applicant: InnnoLux Corporation
    Inventors: Kuei-Sheng Chang, Po-Yang Chen, Kuo-Jung Wu, I-An Yao, Wei-Cheng Lee, Hsien-Wen Huang
  • Publication number: 20240136825
    Abstract: Disclosed is a battery system, including several parallel-connected battery clusters, each battery cluster being connected to a power conversion system via a battery bus, and any one of battery clusters includes several series-connected battery packs; pack equalizers, corresponding to the battery packs on a one-to-one basis, a first end of the pack equalizer being connected to two ends of a corresponding battery pack, and a second end thereof being connected to a power source; and a cluster equalizer, a first end of the cluster equalizer being connected in series to the battery packs, and a second end thereof being connected to the power source. According to the battery system, the pack equalizer is used between the battery packs to regulate the equalization of the battery packs in each cluster; in addition, each battery cluster is connected to the cluster equalizer to realize equalization regulation of the battery cluster.
    Type: Application
    Filed: June 27, 2021
    Publication date: April 25, 2024
    Applicant: Envision Energy CO., LTD
    Inventors: Wei ZENG, Jin WEN
  • Publication number: 20240136117
    Abstract: A multi-phase coupled inductor includes a first iron core, a second iron core, and a plurality of coil windings. The first iron core includes a first body and a plurality of first core posts. The plurality of first core posts are connected to the first body. The second iron core is opposite to the first iron core. The second iron core and the first body are spaced apart from each other by a gap. The plurality of coil windings wrap around the plurality of first core posts, respectively. Each of the coil windings has at least two coils.
    Type: Application
    Filed: October 1, 2023
    Publication date: April 25, 2024
    Inventors: HUNG-CHIH LIANG, PIN-YU CHEN, HANG-CHUN LU, YA-WEN YANG, YU-TING HSU, WEI-ZHI HUANG
  • Patent number: 11966628
    Abstract: A memory device, includes a memory array for storing a plurality of vector data each of which has an MSB vector and a LSB vector. The memory array includes a plurality of memory units each of which has a first bit and a second bit. The first bit is used to store the MSB vector of each vector data, the second bit is used to store the LSB vector of each vector data. A bit line corresponding to each vector data executes one time of bit-line-setup, and reads the MSB vector and the LSB vector of each vector data according to the bit line. The threshold voltage distribution of each memory unit is divided into N states, where N is a positive integer and N is less than 2 to the power of 2, and the effective bit number stored by each memory unit is less than 2.
    Type: Grant
    Filed: June 2, 2022
    Date of Patent: April 23, 2024
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Wei-Chen Wang, Han-Wen Hu, Yung-Chun Li, Huai-Mu Wang, Chien-Chung Ho, Yuan-Hao Chang, Tei-Wei Kuo
  • Patent number: 11968906
    Abstract: A method for fabricating a semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a contact hole in the first IMD layer; forming a bottom electrode layer in the contact hole; forming a magnetic tunneling junction (MTJ) stack on the bottom electrode layer; and removing the MTJ stack and the bottom electrode layer to form a MTJ on a bottom electrode. Preferably, the bottom electrode protrudes above a top surface of the first IMD layer.
    Type: Grant
    Filed: May 25, 2020
    Date of Patent: April 23, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Jin-Yan Chiou, Wei-Chuan Tsai, Hsin-Fu Huang, Yen-Tsai Yi, Hsiang-Wen Ke
  • Patent number: D1026916
    Type: Grant
    Filed: January 5, 2022
    Date of Patent: May 14, 2024
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Hao-Jen Fang, Kung-Ju Chen, Wei-Yi Chang, Chun-Chieh Chen, Chih-Wen Chiang, Sheng-Hung Lee