Abstract: The present application provides a method for forming a chip package and a chip package. The method comprises mounting at least one chipset including at least first and second chips on a carrier with front surface of the chips face away from the carrier; attaching an interconnection device to the front surfaces of the first and second chips to enable electrically connections between the chips; forming a molded encapsulation layer whereby the first chip, the second chip and the interconnection device are embedded or partially embedded in the molded encapsulation layer; thinning one side of the molded encapsulation layer away from the carrier to expose first bumps on the first and second chips; forming second bumps on a surface of one side of the molded encapsulation layer where the first bumps are exposed; and removing the carrier. Thus, a flexible, efficient and low-cost packaging scheme is provided for multi-chip connection.

Abstract: The present application provides a method for forming chip packages and a chip package. The method comprises arranging a plurality of interconnect devices at intervals on a surface of a carrier and assembling a plurality of chipsets over the interconnect devices. Each chipset comprises at least two chips electrically connected through an interconnect device. A front surface of each chip facing the carrier is provided with a plurality of first bumps. The method further comprises forming a molded package layer whereby the plurality of chipsets and the plurality of interconnect devices are embedded in the molded package layer; removing the carrier and thinning the molded package layer to expose the first bumps; forming second bumps on the surface on one side of the molded package layer where the first bumps are exposed; and dicing the molded package layer to obtain a plurality of package units. Thus, a flexible and low-cost packaging scheme is provided for multi-chip interconnection.

Abstract: The present disclosure provides a chip interconnecting method, an interconnect device and a method for forming a chip interconnection package. The method comprises arranging at least one chipset on a carrier, each chipset including at least a first chip and a second chip. A contact surface (or diameter) of each of the first bumps is smaller than that of any of the second bumps. The method further comprises attaching an interconnect device to the first chip and the second chip, the interconnect device including first pads for bonding to corresponding bumps on the first chip and second pads for bonding to corresponding bumps on the second chip. Attaching the interconnect device includes aligning the plurality of first pads with the corresponding bumps on the first chip whereby the plurality of second pads are self-aligned for bonding to the plurality of second bumps.

Abstract: The present disclosure provides a method for forming a semiconductor package and a semiconductor package. The method comprises providing a semiconductor wafer with at least one semiconductor device formed thereon, the at least one semiconductor device comprising a plurality of metal bond pads formed on the semiconductor wafer. The method further comprises forming a first photoresist layer having a first opening directly above at least a portion of a first metal bond pad; forming a first metal feature of a first height in the first opening; removing the first photoresist layer; forming a second photoresist layer having a second opening directly above at least a portion of the second metal bond pad; forming a second metal feature of a second height in the second opening; and removing the second photoresist layer. Using the method, metal bumps having different heights and different sizes can be formed in a controlled manner.

Abstract: A method of forming a package is provided. The method comprises assembling on a carrier a stack of chip layers including a plurality of first chip layers and a second chip layer; encapsulating the stack of chip layers in a molding compound; removing the carrier to form a package main body; forming a redistribution layer on an exposed side of a first chip layer; and dividing the package main body to form a plurality of packages. Each first chip layer includes first chips and chip couplers. A chip package includes at least one chip stack and at least one chip coupler stack on a singulated redistribution layer. Each chip stack includes at least one chip from each chip layer, and each chip coupler stack includes at least one chip coupler and/or at least one chip coupler segment from each of the first chip layers.

Abstract: A method of forming a package comprises forming a stack of chip layers on a carrier. The stack of chip layers including at least a first chip layer over the carrier and a second chip layer over the first chip layer. The first chip layer includes a plurality of first chips facing the carrier and a plurality of chip couplers. The second chip layer includes a plurality of second chips facing the first chip layer. The method further comprises encapsulating the stack of chip layers in a molding compound, removing the carrier to expose the front side of the first chip layer, forming a redistribution layer on the front side of the first chip layer and bumps on the redistribution layer, and dividing the stack of chips and the redistribution layer to form a plurality of the packages. A chip package thus formed include a stack of chips and one or more chip connectors on a singulated redistribution layer.

Abstract: A semiconductor packaging method, a semiconductor assembly and an electronic device comprising the semiconductor assembly are described herein. The semiconductor packaging method comprises providing at least one semiconductor device and a carrier board. A plurality of first alignment solder parts are formed on an active surface of each semiconductor device in addition to connection terminals. A plurality of second alignment solder parts are formed on a surface of the carrier board.

Abstract: A semiconductor packaging method, a semiconductor assembly and an electronic device comprising the semiconductor assembly are disclosed herein. The semiconductor packaging method comprises providing at least one semiconductor device and a carrier board. A plurality of first alignment solder parts are formed on a passive surface of the semiconductor device, and a plurality of corresponding second alignment solder parts are formed on the carrier board. The method further comprises forming a plurality of alignment solder joints by aligning and soldering the first alignment solder parts to respective ones of the second alignment solder parts whereby the semiconductor device is aligned and fixed to the carrier board; encapsulating the at least one semiconductor device to form a molded package body; sequentially forming a redistribution layer and external terminals on the molded package body so that the connection terminals are connected to the external terminal through the interconnection layer.

Abstract: A method of forming a package comprises forming a stack of chip layers. Each chip layer has a front side facing away from the carrier substrate. A first chip layer includes a plurality of first chips having first chip contacts on the front side of the first chip layer and chip couplers having through vias. A second chip layer includes a plurality of second chip having second chip contacts on the front side of the second chip layer and coupled to respective ones of at least a first subset of the through vias. The method further comprises forming a redistribution layer on the front side of the first chip layer and dividing the stack of chip layers and the redistribution layer to form a plurality of chip packages. A chip package thus formed include a stack of chips and one or more chip connectors on a singulated redistribution layer.

Abstract: An optoelectronic device includes a semiconductor substrate and a first stack of epitaxial layers, which are disposed over the semiconductor substrate and are configured to function as a photodetector, which emits a photocurrent in response to infrared radiation in a range of wavelengths greater than 940 nm. A second stack of epitaxial layers is disposed over the first stack and configured to function as an optical transmitter with an emission wavelength in the range of wavelengths greater than 940 nm.

Abstract: A portable temperature regulation device includes a wearing body and first and second main bodies rotatably connected to the wearing body. The first and second main bodies each include a first housing in which a first receiving chamber is formed to receive a first fan therein. The first main body further includes a first air passage in communication with the first receiving chamber, a first air outlet communicating the first air passage and outside, an air inlet in communication with the first receiving chamber. The first and second main bodies are rotatably connected to the wearing body by a rotation structure. When it needs to fold for storage, the first and second main bodies can be rotated to a folded state, so as to reduce the size of the portable temperature regulation device for easy storage by a user.

Abstract: A portable temperature regulation device includes a wearing body and first and second main bodies rotatably connected to the wearing body. The first and second main bodies each include a first housing in which a first receiving chamber is formed to receive a first fan therein. The first main body further includes a first air passage in communication with the first receiving chamber, a first air outlet communicating the first air passage and outside, an air inlet in communication with the first receiving chamber. The first and second main bodies are rotatably connected to the wearing body by a rotation structure. When it needs to fold for storage, the first and second main bodies can be rotated to a folded state, so as to reduce the size of the portable temperature regulation device for easy storage by a user.

Abstract: A portable blowing device includes a body and fans arranged in the body. Air channels are arranged in the body and extend in the length direction of the body to allow airflow to pass through. Wind shields are arranged in the air channels, and a periphery of the wind shield is closely connected with a side wall of the air channel so that a sub-air channel is formed between the wind shield and the side wall of the air channel. Air outlets are formed in the side wall for communicating with outside and the sub-air channel, and airflow generated by the fan can enter the sub-air channel and then exits the air outlets. Because of the reduced volume of the sub-air channel, the airflow is concentrated after entering the sub-air channel, and airflow exiting the air outlets is strengthened, so that the cooling effect and the user experience are improved.

Abstract: A portable blowing device includes a body and fans arranged in the body. Air channels are arranged in the body and extend in the length direction of the body to allow airflow to pass through. Wind shields are arranged in the air channels, and a periphery of the wind shield is closely connected with a side wall of the air channel so that a sub-air channel is formed between the wind shield and the side wall of the air channel. Air outlets are formed in the side wall for communicating with outside and the sub-air channel, and airflow generated by the fan can enter the sub-air channel and then exits the air outlets. Because of the reduced volume of the sub-air channel, the airflow is concentrated after entering the sub-air channel, and airflow exiting the air outlets is strengthened, so that the cooling effect and the user experience are improved.

Abstract: A portable blowing device includes a body and fans arranged in the body. Air channels are arranged in the body and extend in the length direction of the body to allow airflow to pass through. Wind shields are arranged in the air channels, and a periphery of the wind shield is closely connected with a side wall of the air channel so that a sub-air channel is formed between the wind shield and the side wall of the air channel. Air outlets are formed in the side wall for communicating with outside and the sub-air channel, and airflow generated by the fan can enter the sub-air channel and then exits the air outlets. Because of the reduced volume of the sub-air channel, the airflow is concentrated after entering the sub-air channel, and airflow exiting the air outlets is strengthened, so that the cooling effect and the user experience are improved.

Abstract: A closed-loop stepper motor control system, drive device and automation device, wherein the system comprises a microprocessor (1) compatible with EtherCAT communication protocol functions, an external interface circuit (2) connected to the said microprocessor (1) and communication interface unit (3); the said microprocessor (1) is also connected to a drive circuit (4), current testing circuit (5), as well as an encoder feedback circuit (6); the said communication interface unit (3) is mutually connected to the said microprocessor (1) through the physical layer communication circuit (31); the said microprocessor (1) is also mutually connected to the power supply circuit (7) that provides stable power supply voltage.

Abstract: A stepper motor driver with brake drive, a drive device and an automation device are disclosed. The stepper motor driver comprises a microprocessor (1) embedded with a communication protocol, an external interface unit (3) mutually connected to the microprocessor (1) and a communication interface circuit (2); the microprocessor (1) is also connected to a drive control circuit (4) and a brake device (5), and the brake device (5) is mutually connected to the external interface unit (3); the microprocessor (1) is also mutually connected to a power supply circuit (13) that provides a stable power supply voltage. The stepper motor driver has such advantages as simple structure, high capacity to resist interference, high effectiveness, low cost, and ease in maintenance.

Abstract: An optoelectronic device includes a semiconductor substrate and an array of emitters disposed on the substrate, including at least first emitters disposed in a central zone of the array and second emitters disposed in at least one peripheral zone of the array, surrounding the central zone. The array includes at least one cathode and at least one anode disposed on opposing sides of the emitters. The first emitters have a first resistance between the at least one cathode and the at least one anode, and the second emitters have a second resistance, greater than the first resistance, between the at least one cathode and the at least one anode. A drive circuit is coupled to apply a selected voltage between the at least one cathode and the at least one anode so as to cause the emitters to emit optical radiation.

Abstract: An optoelectronic device includes a semiconductor substrate and a first stack of epitaxial layers, which are disposed over the semiconductor substrate and are configured to function as a photodetector, which emits a photocurrent in response to infrared radiation in a range of wavelengths greater than 940 nm. A second stack of epitaxial layers is disposed over the first stack and configured to function as an optical transmitter with an emission wavelength in the range of wavelengths greater than 940 nm.

Abstract: An optoelectronic device includes a semiconductor substrate and an array of optoelectronic cells, formed on the semiconductor substrate. The cells include first epitaxial layers defining a lower distributed Bragg-reflector (DBR) stack; second epitaxial layers formed over the lower DBR stack, defining a quantum well structure; third epitaxial layers, formed over the quantum well structure, defining an upper DBR stack; and electrodes formed over the upper DBR stack, which are configurable to inject an excitation current into the quantum well structure of each optoelectronic cell. A first set of the optoelectronic cells are configured to emit laser radiation in response to the excitation current. In a second set of the optoelectronic cells, interleaved with the first set, at least one element of the optoelectronic cells, selected from among the epitaxial layers and the electrodes, is configured so that the optoelectronic cells in the second set do not emit the laser radiation.