Abstract: A superscalar microprocessor is provided which includes a integer functional unit and a floating point functional unit that share a high performance main data processing bus. The integer unit and the floating point unit also share a common reorder buffer, register file, branch prediction unit and load/store unit which all reside on the same main data processing bus. Instruction and data caches are coupled to a main memory via an internal address data bus which handles communications therebetween. An instruction decoder is coupled to the instruction cache and is capable of decoding multiple instructions per microprocessor cycle. Instructions are dispatched from the decoder in speculative order, issued out-of-order and completed out-of-order. Instructions are retired from the reorder buffer to the register file in-order. The functional units of the microprocessor desirably accommodate operands exhibiting multiple data widths.

Abstract: A processor core for supporting the concurrent execution of mixed integer and floating point operations includes integer functional units (110) utilizing 32-bit operand data and a floating point functional unit (22) utilizing up to 82-bit operand data. Eight operand busses (30, 31) connect to the functional units to furnish operand data, and five result busses (32) are connected to the functional units to return results. The width of the operand busses is 41 bits, which is sufficient to communicate either integer or floating point data. This is done using an instruction decoder (18) to apportion a floating point operation which operates on 82-bit floating point operand data into multiple suboperations each associated with a 41-bit suboperand. The operand busses and result busses have an expanded data-handling dimension from the standard integer data width of 32 bits to 41 bits for handling the floating point operands.

Abstract: A coarse/fine alignment system and method for boresighting high energy, laser pulses onto ballistic missiles in their boost phase. A ground based, common optical aperture laser separator, a mosaic array sensor, and a controller are cooperative to align bursts of light of a ground based laser with a beacon laser of a satellite reciprocally along an uplink therebetween so that the wavelength of the bursts and the wavelength of the beacon laser are the same wavelength. The principle of propagation reciprocity operates to provide ultra high alignment accuracy. Light provided along the reciprocal optical path provides boresight blooming autocollimation and an ultra high pointing angle resolution. An inertial target tracker provides spacial coordinates and angular rate coordinates of remote targets sited by the tracker. A single mosaic array sensor and associated systems are operative to provide pseudo-star, target spot, and other sensor spots compensated for vibration and other noise phenomena.

Abstract: A space-based command guidance controller and controlled deliverable traveling at speeds of about Mach five are cooperative to cause the deliverable to follow a coherent designator beam controlled by the space-based command guidance controller to be delivered to a target location, eventually designated by the beam along an over-the-horizon trajectory, and into a target thereat with surgical-like precision. The command guidance controller includes an optical tracker and coherent designator laser assembly and an inertially-stabilized tracker that are cooperative to produce a command guidance signal representative of that controlled deliverable maneuver that enables the controlled deliverable, upon the execution thereof, to conform its trajectory to the intended trajectory, and eventually, to impact the intended target.

Abstract: An attitude sensing system utilizing simplified techniques and apparatus includes a Kalman filter which receives signals from an inertial measurement unit, a GPS receiver, and an integrated optical assembly. The output vector of the filter includes estimates of attitude misalignments and estimates of gyro drifts corresponding to the axes of the inertial measurement unit. The optical assembly includes a sensor array providing signals to the filter representing detection of the Earth's horizon or the center of the Sun. More particularly, a local vertical vector, computed from fore and aft detections of the Earth's horizon, is used in combination with GPS received signals to initially determine attitude by means of gyrocompassing. This attitude information is thereafter maintained by the inertial measurement unit and azimuth error resulting from drift of the inertial measurement unit and the initial gyrocompassing error is corrected by detections of the Earth's horizon and the Sun.

Abstract: One or more strap-down star tracker modules and a strap-down gyro module cooperate to provide a high-performance and low-cost inertial guidance system especially well suited for ballistic missiles. The one or more star tracker modules include an alignment laser that cooperates with one or more gyro module autocollimation mirrors to measure three-axis bending and twist between the one or more strap-down star tracker modules and the strap-down gyro module. The one or more strap-down star tracker modules and the strap-down gyro module respectively determine inertial angle independently of one another. The strap-down gyro module is compensated for gyro drift whenever any difference remains between the inertial angle measured thereby and the same inertial angle measured by the one or more star tracker modules after isolating the contribution thereto of the measured three-axis bending and twist.

Abstract: A processing system is configured for providing an external in circuit emulator with an internal execution state resulting from the execution by a first processor of an internal instruction stored in an internal instruction cache. The processing system includes a second processor which includes an internal instruction cache for also storing the internal instructions. The second processor is coupled to the first processor in a master/slave configuration to enable the second processor to duplicate the instruction executions of the first processor. The second processor includes an output for providing the internal execution state which is coupled to the in circuit emulator by an external address bus for providing the internal execution parameter to the in circuit emulator.

Abstract: Methods and apparatus are disclosed for transferring data to and from the Local Bus of a reduced instruction set computer (RISC) system, to which a first set of high performance devices, including at least one central processor ("CPU"), is attached, and a Remote Bus, to which a second set of relatively lower performance devices is attached, in a manner that does not limit the RISC processor's performance. According to the preferred embodiment of the invention, a RISC architecture is disclosed that includes a novel data transfer controller ("DTC"), or set of DTCs, suitable for performing the aforesaid data transfer function between the high performance Local Bus and one or more Remote Buses to which complete subsystems or peripherals, typically having different (and lower) performance characteristics, are attached. The resulting RISC arthitecture permits commercially available peripherals and subsystems to be used with high performance RISC processors without limiting RISC system performance.

Abstract: A processing system provides efficient accessing by a processor of a memory during a sequential memory access. The processing system includes a memory having a plurality of storage locations, each being addressable at a corresponding different storage address, a processor coupled to the memory for addressing the memory storage locations for accessing the storage locations and control means coupled to the memory and to the processor. The control means is responsive to a sequential access by the processor for causing the processor to address selected spaced apart ones of the storage locations in order and is arranged to access the other memory locations in order between the processor addresses to provide an access rate of one word of information per system clock cycle.

Abstract: A processor having improved exception handling capability handles second level exceptions with reduced exception latency. The processor processes instructions in order through a plurality of serial stages. A first set of registers continuously tracks each instruction as it advances from stage to stage. An exception handles processes first level exception conditions and precludes updating of the first set of registers when it processes first level exception conditions to permit the processor to restart at the point of a first level exception condition. A second set of registers continuously tracks the instruction in tandem with the first set of registers, but is updatable during the processing of first level exception conditions by the exception handles.

Abstract: A new and improved external memory accessing system for use in a microprocessor. The system includes a physical address cache for storing a plurality of entries including register numbers and corresponding translated external memory address locations which were used for execution of previous load instructions. The system further includes means responsive to a current load instruction for determining if the address of the register specified in the load instruction is within the physical address cache and means for conveying to the external memory, at the beginning of the execution stage of the load instruction, a previously translated external memory physical address corresponding to a specified register stored in the physical address cache. Also disclosed is a new and improved address generator for generating a new translated external memory physical address which is conveyed to the external memory and to the physical address cache for updating the physical address cache.

Abstract: Method and apparatus for use with dot-matrix printers to ensure that the maximum heat dissipation of critical components associated with the printhead is not exceeded during high density printing. The number of dots to be printed are determined by a counting technique which takes into consideration the thermal time constant of a critical component and the filter time constant of the power controlling or supplying components. These considerations allow the counting of output dots to be accurately transformed by a single dot power conversion factor into an accurate representation of the power in the critical components. The dot counts are divided into time intervals dependent upon a filter time constant and a thermal time constant. The dot counts are squared, summed and rooted to produce an RMS value which accurately predicts the power which produces the heat dissipation in the critical components.

Abstract: Methods and apparatus are disclosed for realizing an integrated cache unit (ICU) comprising both a cache memory and a cache controller on a single chip. The novel ICU is capable of being programmed, supports high speed data and instruction processing applications in both Reduced Instruction Set Computers (RISC) and non-RISC architecture environments, and supports high speed processing applications in both single and multiprocessor systems. The preferred ICU has two buses, one for the processor interface and the other for a memory interface. The ICU support single, burst and pipelined processor accesses and is capable of operating at frequencies in excess of 25 megahertz, achieving processor access times of two cycles for the first access in a sequence, and one cycle for burst mode or piplined accesses. It can be used as either an instruction or data cache with flexible internal cache organization.

Abstract: Apparatus and method are disclosed enabling to register vectors respectively representative of directed energy pointing direction and targeted object pointing direction to allow rapid re-targeting boresight alignment transfer of a space-based neutral particle beam to targeted ballistic missile trajectories independently of relative reference frame vector measurement uncertainty arising from platform vibration and, among other things, space-noise.

Abstract: A method and apparatus are described for expanding the capability of an instruction prefetch buffer. The method and apparatus enables the instruction prefetch buffer to distinguish between old prefetches that occurred before a branch in an instruction stream and new prefetches which occurred after the branch in the instruction stream. A control tag is generated each time a request for an instruction is sent to a storage. The returning instruction has appended thereto the original control tag which is then compared to the current value of control tag in the instruction prefetch buffer. If the two values match, then this is an indication that a branch has not occurred and the instruction is still required. However, if the two values of the control tag are not equal, then this is an indication that a branch in the instruction stream has occurred and that the instruction being sent from storage to the buffer is no longer required.

Abstract: Methods and apparatus are disclosed for transferring data to and from a first bus, to which a first set of high performance devices, including at least one central processing unit ("CPU") is attached, and a second bus, to which a second set of relatively lower performance devices is attached. More particularly the invention accomplishes the above transfer function in a manner that facilitates communication between the first and second set of devices from the compartively lower performance of the second set of devices. According to the preferred embodiment of the invention, a data transfer controller i.e., ("DTC") is disclosed that includes a set of direct memory access ("DMA") channels and an input/output controller comprising a set of address mapped I/O ports.

Abstract: A super-scaler processor is disclosed wherein branch-prediction information is provided within an instruction cache memory. Each instruction cache block stored in the instruction cache memory includes branch-prediction information fields in addition to instruction fields, which indicate the address of the instruction block's successor and information indicating the location of a branch instruction within the instruction block. Thus, the next cache block can be easily fetched without waiting on a decoder or execution unit to indicate the proper fetch action to be taken for correctly predicted branching.

Abstract: A multiple instruction decoder includes an input latch for receiving a plurality of logic instructions, wherein the plurality of logic instructions include N register-operand identifiers; arbitration logic coupled to the input latch for arbitrating read port contentions by the N register-operand identifiers for M available read ports (where M is less than N) based on arbitration data corresponding to each of the logic instructions, and for generating control signals indicative thereof; and a multiplexing unit for selectively supplying the N register-operand identifiers to the M available read ports in response to the control signals generated by the arbitration logic.

Abstract: The present invention is directed to a conventional data processing system having a CPU and at least one external unit such as the main storage unit acquiring data from or providing data to the CPU and I/O bus for the transfer of data between the CPU and the external unit. The apparatus of the present invention provides for transfers to and from this external unit, e.g., main storage being overlapped with a register to register data transfer routinely carried out in the CPU to implement various CPU operations and computation functions. The CPU includes apparatus for transferring data to or from said external unit over the I/O bus during synchronized time cycles. The CPU also includes local storage apparatus which comprise a plurality of registers as well as expedients for transferring data from register to register. Control apparatus controls the register to register data transfer so that such transfers are conducted during time cycles coincident with the transfer of data to or from the external storage unit.