Abstract: A body portion is supported in upright position by a support stem and has wind propelling blades arranged to rotatably drive the body portion when subjected to air currents. The body portion has front and rear surfaces one of which may support a rear view mirror and the other of which may support a reflector. The body portion has a lock nut for holding it stationary on the stem, for allowing rotation thereof when released. The body portion has forward and rearward as well as lateral adjustable positioning on the stem, and the stem has lateral positioning on a bracket that mounts it on a vehicle.

Abstract: A circuit for limiting the effect of overshoot in a transformer of the type having a primary winding and a secondary winding. The secondary winding is coupled to a load and the circuit has an output. An auxiliary or ballistic winding is operatively connected to the transformer and is adapted to generate a winding voltage which varies in response to a voltage generated across the primary winding. An electronic switch, preferably a transistor, is interposed between the ballistic winding and the output of the circuit. The switch is capable of being disposed in a first position or a second position. In one preferred embodiment, the winding voltage is communicated to the circuit output when the switch is in the first position. An actuating arrangement is coupled with both of the ballistic winding and the electronic switch. The electronic switch is disposed into the first position by the actuating arrangement a predetermined time interval after the winding voltage has exceeded a predetermined reference voltage.

Abstract: Methods and apparatus are set forth for transferring data to and from a first bus, to which a first set of high performance devices, including at least one central processing unit ("CPU") is attached, and a second bus, to which a second set of relatively lower performance devices is attached. The aforesaid transfer is accomplished in a manner that facilitates communication between the first and second set of devices while insulating the performance of the first set of devices from the comparatively lower performance of the second set of devices. According to the preferred embodiment of the invention, an input/output controller i.e., ("IOC") is disclosed that includes a set of address mapped I/O ports. The I/O ports may be used to transfer data between the high performance channel (hereinafter referred to as the "Local Bus") coupled to the CPU in a reduced instruction set computer (RISC) system and a typically lower performance, peripheral bus (hereinafter referred to as a "Remote Bus").

Abstract: A streamlined instruction processor processes data in response to a program composed of prespecified instructions in pipeline cycles. The processor comprises an instruction fetch unit, including an instruction interface adapted for connection to an instruction memory and for fetching instructions from the instruction memory. The instruction fetch unit includes an instruction prefetch buffer coupled to the instruction interface for buffering a sequence of instructions supplied to the instruction interface. A branch target cache is coupled with the prefetch buffer for storing sets of instructions retrieved from a corresponding set of locations in the instruction memory, having sequential instruction addresses. The first instruction in each such set is a branch target instruction in the program.In addition, an execution unit including a data interface adapted for connection to the data memory, executes the instructions in pipeline cycles.

Abstract: In a data processing system, particularly one implemented by a microprocessor, apparatus is provided for bypassing the main parallel information bus between the processor and main storage unit by a serial information bus for testing purposes. Serial test information is applied through the serial information bus to a storage control unit which interfaces the processor and storage unit. The control includes circuitry for converting the information from the serial bus into the parallel format of the data which is provided from the processor along the main parallel bus. The test information applied has the same commands and address structure as the information output from the central processor. As a result, when the serial test information is converted to parallel format, by the apparatus, it will be indistinguishable from parallel data applied directly from the processor along the parallel bus.

Abstract: Methods and apparatus are disclosed for transferring data to and from a first bus, to which a first set of high performance devices, including at least one central processing unit ("CPU") is attached, and a second bus, to which a second set of relatively lower performance devices is attached. More particularly the invention accomplishes the transfer function in a manner that facilitates communication between the first and second set of devices from the comparatively lower performance of the second set of devices. Direct memory access ("DMA") apparatus and methods are disclosed, including a set of direct memory access channels. The DMA channels may be used to transfer data between the high performance channel (hereinafter referred to as the "Local Bus") coupled to the CPU in a reduced instruction set computer (RISC) system and a typically lower performance, peripheral bus (hereinafter referred to as a "Remote Bus").

Abstract: An adjustable roller assembly for sliding doors including a housing adapted to be snap-fit into a recess provided in the upper or lower surface of a door frame, the housing defining a cavity which is open at the lower end. A roller carrier is mounted in the housing cavity and is vertically adjustable with respect to the housing. The lower end of the roller carrier defines circular flanges in which is rotatably mounted a roller having an integral hub. A camming arrangement associated with the roller carrier is accessible for adjustment from the side of the door frame and is operable to adjust the vertical position of the roller carrier and roller to adjust the slack between the door and the track upon which the roller is adapted to ride.

Abstract: Methods and apparatus for realizing a high performance interface between a processor, constituting part of a reduced instruction set computer (RISC) system, and a set of devices, including memory means. According to the invention, the interface includes three independent buses. A shared processor output bus, a processor input instruction bus, and a bidirectional data bus. The shared processor output address bus coupled the processor and the computer's memory. This bus carries both instructon and data access signals being transmitted by the processor to the memory. The processor input instruction bus also couples the processor and the computer's memory means, but carries instruction signals being transmitted from the memory to the processor. The bidirectional data bus provides a signal path for carrying data signals being transmitted by the memory to the processor and vice-a-versa.

Abstract: A method of operating a data processing system using virtual memory in which virtual memory addresses are formed by a base register value and a displacement value and are mapped to real memory addresses includes the steps of adding the base register value content and the displacement value, and simultaneously with the adding operation, performing a translation of the base register value to produce a virtual address corresponding to the base register value.

Abstract: Methods and apparatus are disclosed that facilitate the testing and development of computer systems that include at least one single chip microprocessor. In particular, a parallel test interface is described that allows an external test unit to (1) directly load instructions into the microprocessor under test utilizing the existing bus structure of the computer system; (2) step the processor through preselected test instruction sequences; (3) monitor processor states in both the processor's test and normal execution modes; and (4) halt and resume normal instruction processing. According to the invention, the microprocessor test interface comprises a plurality of dedicated CPU status output pins and a plurality of dedicated CPU control input pins, used by the test unit in combination with the existing bus structure of the computer system to provide the desired test facility for the single chip microprocessor.

Abstract: A microprogrammed parallel processor including a plurality of subprocessors operates under the control of microinstructions. Each microinstruction contains a plurality of micro-operations each of which requires one or more subprocessors for execution. All micro-operations for which required subprocessors are available are immediately carried out. Any remaining micro-operations within a microinstruction which are not executed due to lack of subprocessor availability are recycled. These remaining micro-operations are executed in subsequent cycles as a required subprocessor becomes available. The entire microinstruction is not recycled but only those portions of it, i.e., the unexecuted micro-operations, are recycled and executed in a subsequent cycle. The microinstruction being executed is stored in a latch until all micro-operations within the microinstruction are executed. At that time, the next microinstruction is fetched into the latch.

Abstract: A baby bottle holder having an enclosure into which the bottle is inserted. A curved surface of the holder permits rocking of the holder upon the bottle being emptied. A weight in the holder imparts rocking movement to the holder upon termination of nursing effort by the infant. An internal wall of the holder insulates the bottle as well as defines air passageways to ease bottle insertion and removal.

Abstract: Apparatus is provided for testing a data processing system which includes a microprocessor, the testing occurring with the microprocessor in place in the system. The apparatus comprises: a support microprocessor for controlling the testing, a serial-to-parallel and parallel-to-serial converter connected between the support microprocessor and the system microprocessor, means for supplying a series of level sensitive scan design (LSSD) test signals from the support microprocessor through the converter to the system microprocessor, and means for returning the results of the level sensitive scan design test signals from the system microprocessor through the converter to the support microprocessor.

Abstract: An agricultural earth engaging implement formed from two metal plate sections. One piece forms a narrow profile shaft and the other forms the earth engaging portion. The shaft is formed to provide a tapered cavity for receiving a tine and the implement is held on to the tine by frictional forces.

Abstract: Means including a single comparatively low-power laser and cooperative optics are disclosed for both designating and boresighting a comparatively high-power laser with an intended target object.

Abstract: A high speed register file for use by an instruction processor suitable for reduced instruction-set computers (RISCs) is disclosed which is preferably used with an efficient register allocation method. The register file facilitates the passing of parameters between procedures by dynamically providing overlapping registers which are accessible to both procedures. Each procedure also has a set of "local" registers assigned to it which are inaccessible from other procedures. The register file is divided into a number of blocks and a protection register stores a word which proscribes access by a particular procedure or task to certain blocks. In this manner, an instruction processor using the register file can operate on multiple tasks maintaining the integrity of each from undesired changes occuring in the others.

Abstract: A method and apparatus expands the capability of an instruction prefetch buffer. The method and apparatus enables the instruction prefetch buffer to distinguish between old prefetches that occurred before a branch in an instruction stream and new prefetches which occurred after the branch in the instruction stream. A control tag is generated each time a request for an instruction is sent to a storage. The returning instruction has appended thereto the original control tag which is then compared to the current value of control tag in the instruction prefetch buffer. If the two values match, then this is an indication that a branch has not occurred and the instruction is still required. However, if the two values of the control tag are not equal, then this is an indication that a branch in the instruction stream has occurred and that the instruction being sent from storage to the buffer is no longer required.

Abstract: A low diffraction-feedback high-energy laser system includes an injection laser, and a master power amplifier (MOPA). The master oscillator power amplifier preferably includes a convex and a concave cavity reflector. A sensor mounted to the convex reflector is operative to provide a signal indication of cavity turbulence.

Abstract: A low diffraction-feedback high-energy laser system includes an injection laser, a master oscillator power amplifier (MOPA), and means for aligning the injection laser to the MOPA. The alignment means includes a relay mirror and sensor array cooperative to center the injection laser externally of the cavity, and the alignment means further includes a relay mirror and cooperative optics and sensor to center the injection laser interiorly of the cavity. Means are disclosed preferably for balancing the heat distribution on both sides of one cavity mirror of the master oscillator power amplifier cavity to maintain its figure undistorted against thermal loading. A composite sensor for providing a dual-sensing capability is disclosed including a mosaic array and a superposed quad sensor. The master oscillator power amplifier preferably includes a convex and a concave cavity reflector.

Abstract: A low diffraction-feedback high-energy laser system includes an injection laser, a master oscillator power amplifier (MOPA), and means for aligning the injection laser to the MOPA. A composite sensor for providing a dual-sensing capability is disclosed including a mosaic array and a superposed quad sensor.