Abstract: Circuits, methods, and apparatus that allow signals that are compliant with multiple standards to share a common connector on an electronic device. An exemplary embodiment of the present invention provides a connector that provides signals compatible with a legacy standard in one mode and a newer standard in another mode.

Abstract: Circuits, methods, and apparatus that allow signals that are compliant with multiple standards to share a common connector on an electronic device. An exemplary embodiment of the present invention provides a connector that provides signals compatible with a legacy standard in one mode and a newer standard in another mode.

Abstract: Embodiments of a synchronization circuit, a method for synchronizing clock signals, and electronic devices that include the synchronization circuit or a computer-program product (e.g., software) with instructions for operations in the method are described. This synchronization circuit synchronizes clock signals in different timing domains using state variables. In particular, the synchronization circuit generates a synchronization acquisition curve based on a temporal history of state-variable differences between the clock signals. Next, the synchronization circuit synchronizes the clock signals (without a discontinuous temporal transient in one or more state variables of a dependent one of the clock signals) based on the sum of the synchronization acquisition curve and the state-variable differences between the clock signals.

Abstract: Embodiments of a synchronization circuit, a method for synchronizing clock signals, and electronic devices that include the synchronization circuit or a computer-program product (e.g., software) with instructions for operations in the method are described. This synchronization circuit synchronizes clock signals in different timing domains using state variables. In particular, the synchronization circuit generates a synchronization acquisition curve based on a temporal history of state-variable differences between the clock signals. Next, the synchronization circuit synchronizes the clock signals (without a discontinuous temporal transient in one or more state variables of a dependent one of the clock signals) based on the sum of the synchronization acquisition curve and the state-variable differences between the clock signals.

Abstract: A signal buffering and retiming (SBR) circuit for a plurality of memory devices. A PLL-based clock generator generates a set of phase-shifted clock signals from a received host clock signal. Each of a plurality of phase selectors independently selects a subset of contiguous clock signals from the set of phase-shifted clock signals. Each subset of contiguous clock signals is applied to a different set of one or more verniers, each vernier independently selecting one of the contiguous clock signals as its retiming clock signal for use in generating either (1) an output clock signal or a retimed bit of address or control data for one or more of the memory devices or (2) a feedback clock signal for the PLL-based clock generator. The SBR circuit can be designed to satisfy relatively stringent signal timing requirements related to skew and delay.

Abstract: A system for receiving data on a communication channel. The system examines the state of a bit that was previously received on the channel. If the state of the previously received bit was high, the system looks for a falling edge while receiving a subsequent bit on the channel. Otherwise, the system looks for a rising edge while receiving the subsequent bit on the channel. While looking for a rising edge or looking for a falling edge, the system samples a signal on the channel at discrete time steps within a symbol interval, wherein the symbol interval is a time period during which the signal can change states. The specific discrete time step at which the signal changes state is associated with a specific decoded output symbol. Note that the signal can also convey information by not changing states.

Abstract: A system that selectively couples one or more IC chips to card slots. The system contains a Z-bar switch which includes: a select input; a first IC port coupled to a first IC pin; a second IC port coupled to a second IC pin; a first card slot port coupled to a first card slot pin; and a second card slot port coupled to a second card slot pin. If the select input receives a first control pattern, the Z-bar switch is configured to: couple the first IC port to the first card slot port; and to couple the second IC port to the second card slot port. If the select input receives a second control pattern, the Z-bar switch is configured to: couple the first IC port to the second card slot port; leave the second IC port floating; and to leave the first card slot port floating.

Abstract: A system that transmits signals through a communication channel. During operation, the system receives a sequence of bits for transmission through the communication channel. While transmitting a given bit, the system determines if the given bit has the same state as the previously transmitted bit. If so, the system uses a voltage-mode driver to drive a signal through the communication channel. Otherwise, the system uses a current source coupled to the voltage-mode driver to boost the drive-level of the voltage-mode driver. Note that the current source supplies a current to the communication channel without changing the impedance of the voltage-mode driver. In this way, the present invention compensates for frequency dependant losses in the communication channel without sacrificing impedance matching and without substantially increasing power consumption.

Abstract: Embodiments of the present invention provide a computer system that reduces voltage noise for a processor chip. The computer system includes a package which is configured to be sandwiched between the processor chip and a circuit board. This package has a bottom surface, which is configured to receive electrical connections for power, ground and other signals from the circuit board, and a top surface, which is configured to provide electrical connections for power, ground and the other signals to the processor chip. A plurality of bypass capacitors are integrated into the package and are coupled between the power and ground connections for the processor chip, so that the plurality of bypass capacitors reduce voltage noise between the power and ground connections for the IC device.

Abstract: One embodiment of the present invention provides an apparatus that reduces voltage noise for an integrated circuit (IC) device. This apparatus includes an interposer, which is configured to be sandwiched between the IC device and a circuit board. This interposer has a bottom surface, which is configured to receive electrical connections for power, ground and other signals from the circuit board, and a top surface, which is configured to provide electrical connections for power, ground and the other signals to the IC device. A plurality of bypass capacitors are integrated into the interposer and are coupled between the power and ground connections for the IC device, so that the plurality of bypass capacitors reduce voltage noise between the power and ground connections for the IC device.

Abstract: Embodiments of the present invention provide a computer system that reduces voltage noise for a processor chip. The computer system includes a package which is configured to be sandwiched between the processor chip and a circuit board. This package has a bottom surface, which is configured to receive electrical connections for power, ground and other signals from the circuit board, and a top surface, which is configured to provide electrical connections for power, ground and the other signals to the processor chip. A plurality of bypass capacitors are integrated into the package and are coupled between the power and ground connections for the processor chip, so that the plurality of bypass capacitors reduce voltage noise between the power and ground connections for the IC device.

Abstract: One embodiment of the present invention provides an apparatus that reduces voltage noise for an integrated circuit (IC) device. This apparatus includes a package which is configured to be sandwiched between the IC device and a circuit board. This package has a bottom surface, which is configured to receive electrical connections for power, ground and other signals from the circuit board, and a top surface, which is configured to provide electrical connections for power, ground and the other signals to the IC device. A plurality of bypass capacitors are integrated into the package and are coupled between the power and ground connections for the IC device, so that the plurality of bypass capacitors reduce voltage noise between the power and ground connections for the IC device.

Abstract: An apparatus and method for maintaining a state during a power load change. The apparatus of one embodiment includes a voltage controller coupled to receive a signal from a detector of current change. The detector of current change in this embodiment is coupled to detect change in the current level at a microprocessor and signal a voltage controller of such change, which in turn causes a change in the voltage supplied to the microprocessor. An embodiment of the method comprises using a current detector in detecting current change in a microprocessor, determining according to the current change the power level that is needed to be maintained and increasing the voltage level for a predetermined amount of time to compensate for (any) voltage droop. In an alternative embodiment, a change in power is determined before the change occurs and as such determines the power level needed at the microprocessor.

Abstract: One embodiment of the present invention provides a system that uses encoded memory control signals to reduce pin count on chips that generate and drive memory control signals. During operation, the system receives encoded memory control signals from a memory controller, wherein the memory control signals were encoded to reduce the number of memory control signals, and wherein the encoded memory control signals are received at a buffer chip, which is external to the memory controller. Next, the system decodes the encoded memory control signals on the buffer chip to restore the memory control signals, and then drives the memory control signals from the buffer chip to corresponding memory modules in the system memory. By transferring the memory control signals in encoded form from the memory controller to the buffer chip, fewer pins are required on both the memory controller chip and the buffer chip.

Abstract: One embodiment of the present invention provides capacitive decoupling on the surface of a semiconductor die, instead of providing the decoupling on a package or printed circuit board to which the semiconductor die is attached. In this embodiment, a surface of a semiconductor die includes exposed power and ground conductors, which are electrically coupled to internal power and ground nodes within the semiconductor die. To provide the wafer-level decoupling, a plurality of bypass capacitors are electrically coupled between pairs of exposed power and ground conductors, so that the plurality of bypass capacitors reduce voltage noise between the power and ground conductors on the semiconductor die.

Abstract: A signal buffering and retiming (SBR) circuit for a plurality of memory devices. A PLL-based clock generator generates a set of phase-shifted clock signals from a received host clock signal. Each of a plurality of phase selectors independently selects a subset of contiguous clock signals from the set of phase-shifted clock signals. Each subset of contiguous clock signals is applied to a different set of one or more verniers, each vernier independently selecting one of the contiguous clock signals as its retiming clock signal for use in generating either (1) an output clock signal or a retimed bit of address or control data for one or more of the memory devices or (2) a feedback clock signal for the PLL-based clock generator. The SBR circuit can be designed to satisfy relatively stringent signal timing requirements related to skew and delay.

Abstract: Wire bonding methods and apparatuses are described herein. In one aspect of the invention, an exemplary apparatus includes a plurality of electrically conductive contacts disposed on a surface of the IC device, the plurality of electrically conductive contacts being disposed in at least two rows, a plurality of first return paths formed through some of the plurality of electrically conductive contacts, a plurality of signal paths formed through some of the plurality of electrically conductive contacts, and wherein at least one of the plurality of first return paths are placed between every predetermined number of the plurality of the signal-paths. Other methods and apparatuses are also described.

Abstract: One embodiment of the present invention provides a system that reduces the number of power and ground pins required to drive address signals to system memory. During operation, the system receives address signals associated with a memory operation from a memory controller, wherein the address signals are received at a buffer chip, which is external the memory controller. The system also receives chip select signals associated with the memory operation at the buffer chip. Next, the system uses the chip select signals to identify an active subset of memory modules in the system memory, which are active during the memory operation. The system then uses address drivers on the buffer chip to drive the address signals only to the active subset of memory modules, and not to other memory modules in the system memory.

Abstract: One embodiment of the present invention provides an apparatus that reduces voltage noise for an integrated circuit (IC) device. This apparatus includes an interposer, which is configured to be sandwiched between the IC device and a circuit board. This interposer has a bottom surface, which is configured to receive electrical connections for power, ground and other signals from the circuit board, and a top surface, which is configured to provide electrical connections for power, ground and the other signals to the IC device. A plurality of bypass capacitors are integrated into the interposer and are coupled between the power and ground connections for the IC device, so that the plurality of bypass capacitors reduce voltage noise between the power and ground connections for the IC device.

Abstract: Methods and apparatus for spreading and concentrating information to constant-weight encode data words on a parallel data line bus while allowing communication of information across sub-word paths. In one embodiment, data transfer rates previously obtained only with differential architectures are achieved by only a small increase in line count above single ended architectures. For example, an 18-bit data word requires 22 encoded data lines for transmission, where previously, 16 and 32 lines would be required to transmit un-coded data with single-ended and differential architectures respectively. Constant-weight parallel encoding maintains constant current in the parallel-encoded data lines and the high and low potential driver circuits for the signal lines.