Abstract: An apparatus and method for maintaining a state during a power load change. The apparatus of one embodiment includes a voltage controller coupled to receive a signal from a detector of current change. The detector of current change in this embodiment is coupled to detect change in the current level at a microprocessor and signal a voltage controller of such change, which in turn causes a change in the voltage supplied to the microprocessor. An embodiment of the method comprises using a current detector in detecting current change in a microprocessor, determining according to the current change the power level that is needed to be maintained and increasing the voltage level for a predetermined amount of time to compensate for (any) voltage droop. In an alternative embodiment, a change in power is determined before the change occurs and as such determines the power level needed at the microprocessor.

Abstract: Wire bonding methods and apparatuses are described herein. In one aspect of the invention, an exemplary apparatus includes a plurality of electrically conductive contacts disposed on a surface of the IC device, the plurality of electrically conductive contacts being disposed in at least two rows, a plurality of first return paths formed through some of the plurality of electrically conductive contacts, a plurality of signal paths formed through some of the plurality of electrically conductive contacts, and wherein at least one of the plurality of first return paths are placed between every predetermined number of the plurality of the signal paths. Other methods and apparatuses are also described.

Abstract: Methods and apparatus for spreading and concentrating information to constant-weight encode of data words on a parallel data line bus while allowing communication of information across sub-word paths. In one embodiment, data transfer rates previously obtained only with differential architectures are achieved by only a small increase in line count above single ended architectures. For example, an 18-bit data word requires 22 encoded data lines for transmission, where previously, 16 and 32 lines would be required to transmit un-coded data with single-ended and differential architectures respectively. Constant-weight parallel encoding maintains constant current in the parallel-encoded data lines and the high and low potential driver circuits for the signal lines.

Abstract: Methods and apparatus for spreading and concentrating information are taught. The present invention relates to constant-weight encoding of data words on a parallel data line bus while allowing communication of information across sub-word paths.

Abstract: Methods and apparatus for spreading and concentrating information to constant-weight encode data words on a parallel data line bus while allowing communication of information across sub-word paths. In one embodiment, data transfer rates previously obtained only with differential architectures are achieved by only a small increase in line count above single ended architectures. For example, an 18-bit data word requires 22 encoded data lines for transmission, where previously, 16 and 32 lines would be required to transmit un-coded data with single-ended and differential architectures respectively. Constant-weight parallel encoding maintains constant current in the parallel-encoded data lines and the high and low potential driver circuits for the signal lines.

Abstract: The present invention provides an apparatus and methods for the functionality of an integrated circuit. An exemplary embodiment according to an aspect of the present invention includes a ball grid array having open spaces therein. Within the open spaces, pairs of opposite polarity vias are clustered to minimize current path inductance by exploiting mutual inductance between vias of opposite current flow. In an illustrative embodiment, capacitors are coupled to the vias to further reduce current path inductance.

Abstract: Methods and apparatus for spreading and concentrating information are taught. The present invention relates to constant-weight encoding of data words on a parallel data line bus while allowing communication of information across sub-word paths.

Abstract: The present invention provides an apparatus and methods for the functionality of an integrated circuit. An exemplary embodiment according to an aspect of the present invention includes a ball grid array having open spaces therein. Within the open spaces, pairs of opposite polarity vias are clustered to minimize current path inductance by exploiting mutual inductance between vias of opposite current flow. In an illustrative embodiment, capacitors are coupled to the vias to further reduce current path inductance.

Abstract: A clock distribution apparatus with active phase alignment which makes the incidence of a timing event occur essentially simultaneously at multiple physically remote destinations. The circuit uses traces configured as reflective transmission lines with a matched impedance input. The propagation time of a transmission line is determined by monitoring the current into the transmission line. Variable delays are determined for each transmission line by measuring the actual propagation time and reducing a predetermined maximum delay time by that amount. The variable delay values are stored and used to retard clock edges by the varying amounts so that all clock edges arrive at respective remote destinations at a time equal to the maximum delay time.

Abstract: A clock distribution apparatus with active phase alignment which makes the incidence of a timing event occur essentially simultaneously at multiple physically remote destinations. The circuit uses traces configured as reflective transmission lines with a matched impedance input. The propagation time of a transmission line is determined by monitoring the current into the transmission line. Variable delays are determined for each transmission line by measuring the actual propagation time and reducing a predetermined maximum delay time by that amount. The variable delay values are stored and used to retard clock edges by the varying amounts so that all clock edges arrive at respective remote destinations at a time equal to the maximum delay time.

Abstract: Apparatus for allowing low noise and fast frequency switching of a ferri-resonant oscillator, such as YIG, that uses a coil to control output signal frequency by current level. The apparatus positions an active filter in parallel with the oscillator coil, which can be set to one of two impedance levels. A low impedance level provides low pass filtering of the current to the oscillator coil for low noise operation. A second high impedance level allows fast settling of transients during frequency changes. Once current levels have stabilized, the active filter can then be switched to low impedance mode without creating a significant transient. This facilitates fast frequency switching.

Abstract: A method and structure is provided for phase locking an output signal having, for example, a desired frequency of 2.sup.C Hz with a reference signal having a frequency of 2.sup.A.5.sup.B Hz. The phase comparison is performed at a high frequency in order to minimize phase noise and spurious signals.