Abstract: An electrostatic discharge protection device including the following components is provided. A first PNP BJT includes a P-type region, first and second N-type well regions, first P-type, first N-type, and second P-type doped regions, and an N-type region. An NPN BJT includes first P-type and third N-type well regions, a second N-type doped region, a third P-type doped region, and a third N-type doped region. A second PNP BJT includes the first P-type and third N-type well regions, the third P-type doped region, the third N-type doped region, and a fourth P-type doped region. The second P-type doped region, the first N-type doped region, the third N-type doped region, and the fourth P-type doped region are coupled to a high voltage side terminal. The first P-type doped region, the second N-type doped region, and the third P-type doped region are coupled to a low voltage side terminal.

Abstract: Provided is a semiconductor structure including a first guard ring and a second guard ring. The first guard ring is located in a substrate. The first guard ring includes first doped regions and second doped regions arranged alternately. The first doped regions and the second doped regions have different conductivity types. The second guard ring is located adjacent to the first guard ring. The second guard ring includes third doped regions and fourth doped regions arranged alternately, and mask layers. Each of the third doped regions corresponds to each of the second doped regions. Each of the fourth doped regions corresponds to each of the first doped regions. The third doped regions and the first doped regions have the same conductivity type and are disposed in a staggered manner. The mask layers are respectively disposed on the substrate between the third doped regions and the fourth doped regions.

Abstract: An electrostatic discharge protection device including the following components is provided. A first PNP BJT includes a P-type region, first and second N-type well regions, first P-type, first N-type, and second P-type doped regions, and an N-type region. An NPN BJT includes first P-type and third N-type well regions, a second N-type doped region, a third P-type doped region, and a third N-type doped region. A second PNP BJT includes the first P-type and third N-type well regions, the third P-type doped region, the third N-type doped region, and a fourth P-type doped region. The second P-type doped region, the first N-type doped region, the third N-type doped region, and the fourth P-type doped region are coupled to a high voltage side terminal. The first P-type doped region, the second N-type doped region, and the third P-type doped region are coupled to a low voltage side terminal.

Abstract: Provided is a semiconductor device including a gate structure, a first doped region of a first conductivity type, a plurality of second doped regions of a second conductivity type, a third doped region of the first conductivity type, and a plurality of fourth doped regions of the second conductivity type. The gate structure is located on a substrate. The first doped region is located in the substrate on a first side of the gate structure. The second doped regions are located in the first doped region. The second doped regions are separated from each other. The third doped region is located in the substrate on a second side of the gate structure. The fourth doped regions are located in the third doped region. The fourth doped regions are separated from each other. The second doped regions and the fourth doped regions are disposed alternately.

Abstract: Provided is a semiconductor structure including a first guard ring and a second guard ring. The first guard ring is located in a substrate. The first guard ring includes first doped regions and second doped regions arranged alternately. The first doped regions and the second doped regions have different conductivity types. The second guard ring is located adjacent to the first guard ring. The second guard ring includes third doped regions and fourth doped regions arranged alternately, and mask layers. Each of the third doped regions corresponds to each of the second doped regions. Each of the fourth doped regions corresponds to each of the first doped regions. The third doped regions and the first doped regions have the same conductivity type and are disposed in a staggered manner. The mask layers are respectively disposed on the substrate between the third doped regions and the fourth doped regions.

Abstract: An electrostatic discharge device includes a power clamping circuit and an isolation circuit. The power clamping circuit includes a first Zener diode and a second Zener diode. A cathode of the first Zener diode is coupled to a first power supply line. An anode of the first Zener diode is coupled to an anode of the second Zener diode. A cathode of the second Zener diode is coupled to a second power supply line. The isolation circuit includes a first isolation diode and a second isolation diode. A cathode of the first isolation diode is coupled to the first power supply line. An anode of the first isolation diode is coupled to a cathode of the second isolation diode and a circuit being protected. An anode of the second isolation diode is coupled to the second power supply line.

Abstract: An electrostatic discharge device includes a power clamping circuit and an isolation circuit. The power clamping circuit includes a first Zener diode and a second Zener diode. A cathode of the first Zener diode is coupled to a first power supply line. An anode of the first Zener diode is coupled to an anode of the second Zener diode. A cathode of the second Zener diode is coupled to a second power supply line. The isolation circuit includes a first isolation diode and a second isolation diode. A cathode of the first isolation diode is coupled to the first power supply line. An anode of the first isolation diode is coupled to a cathode of the second isolation diode and a circuit being protected. An anode of the second isolation diode is coupled to the second power supply line.

Abstract: A manufacturing method of a semiconductor structure provides a substrate. A well having a first conductive type and a well having a second conductive type are formed in the substrate, respectively. A body region is formed in the well having the second conductive type. A first doped region and a second doped region are formed in the well having the first conductive type and the body region respectively. The first and second doped regions have same polarities, and a dopant concentration of the second doped region is higher than that of the first doped region. A third doped region is formed in the well having the second conductive type and between the first and second doped regions. The third and first doped regions have reverse polarities. A first field plate is formed on a surface region between the second and third doped regions.

Abstract: A semiconductor device is provided having a dual dielectric layer structure defined by a thin dielectric layer adjacent to a thick dielectric layer. More particularly, a high voltage metal oxide semiconductor transistor having a dual gate oxide layer structure comprising a thin gate oxide layer adjacent to a thick oxide/thin oxide layer may be provided. Such structures may be used in extended drain metal oxide semiconductor field effect transmitters, laterally diffused metal oxide field effect transistors, or any high voltage metal oxide semiconductor transistor. Methods of fabricating an extended drain metal oxide semiconductor transistor device are also provided.

Abstract: A semiconductor device includes high-voltage (HV) and low-voltage (LV) MOS's formed in a substrate. The HV MOS includes a first semiconductor region having a first-type conductivity and a first doping level, a second semiconductor region having the first-type conductivity and a second doping level lower than the first doping level, a third semiconductor region having a second-type conductivity, and a fourth semiconductor region having the first-type conductivity. The first, second, third, and fourth semiconductor regions are arranged along a first direction, and are drain, drift, channel, and source regions, respectively, of the HV MOS. The LV MOS includes the fourth semiconductor region, a fifth semiconductor region having the second-type conductivity, and a sixth semiconductor region having the first-type conductivity.

Abstract: Provided is a semiconductor device, including: a substrate, a well region of a first conductivity type, a field region of a second conductivity type, a first doped region of the first conductivity type, and a second doped region of the second conductivity type. The well region is located in the substrate. The field region is located in the well region. The first doped region is located in the well region of a first side of the field region. The second doped region is located in the field region, wherein the first doped region is at least partially surrounded by the second doped region.

Abstract: Provided is a semiconductor device, including: a substrate, a well region of a first conductivity type, a field region of a second conductivity type, a first doped region of the first conductivity type, and a second doped region of the second conductivity type. The well region is located in the substrate. The field region is located in the well region. The first doped region is located in the well region of a first side of the field region. The second doped region is located in the field region, wherein the first doped region is at least partially surrounded by the second doped region.

Abstract: Provided is a semiconductor device including a gate structure, a first doped region of a first conductivity type, a plurality of second doped regions of a second conductivity type, a third doped region of the first conductivity type, and a plurality of fourth doped regions of the second conductivity type. The gate structure is located on a substrate. The first doped region is located in the substrate on a first side of the gate structure. The second doped regions are located in the first doped region. The second doped regions are separated from each other. The third doped region is located in the substrate on a second side of the gate structure. The fourth doped regions are located in the third doped region. The fourth doped regions are separated from each other. The second doped regions and the fourth doped regions are disposed alternately.

Abstract: A high voltage (HV) device and method for manufacturing the same are provided, at least comprising a substrate, an insulation formed on the substrate, a deep well formed in the insulation, an air layer formed in the insulation and disposed adjacent to the bottom surface of the deep well. A bottom surface of the deep well is spaced apart from the substrate. Also, the air layer, interposed between the deep well and the substrate, is spaced apart from the substrate. In one embodiment, an air layer further communicates with an atmosphere outside the HV device, which facilitates heat dissipation.

Abstract: A semiconductor device formed in a substrate, including a first region, a second region formed over the first region, a third region, a fourth region formed over the third region, and a fifth region formed over the first region and contacting the second region. The first, second, and fourth regions have a first-type conductivity, and constitute drain region, drain electrode, and source region of a metal-on-semiconductor (MOS) structure. The second region has a higher doping level than the first region. The third region has a second-type conductivity and constitutes channel and body regions of the MOS structure. The fifth region has the second-type conductivity and constitutes an emitter region of a bipolar junction (BJ) structure. The second and third regions constitute base and collector regions of the BJ structure.

Abstract: A semiconductor device includes a substrate, a first doped well disposed in the substrate, a second doped well disposed in the substrate adjacent to a first side of the first doped well, a buffer region disposed in the first doped well adjacent to a second and opposite side of the first doped well, a gate structure disposed above the first side of the first doped well and extending along a first horizontal direction, a first contact region disposed in the buffer region toward the second side of the first doped well, a second contact region disposed in the buffer region adjacent to the first contact region, and a doped region disposed in the buffer region under the first contact region.

Abstract: A semiconductor device includes first metal-on-semiconductor (MOS), second MOS, and bipolar junction (BJ) structures formed in a substrate. The first MOS structure includes first drain, first channel, and first source regions arranged along a first direction. The first MOS structure further includes a drain electrode formed over and conductively coupled to the first drain region, and a body region formed below and conductively coupled to the channel region. The second MOS structure includes second drain, second channel, and second source regions arranged along a second direction different from the first direction. The BJ structure includes emitter, base, and collector regions. The first source region and the second drain region share a first common semiconductor region in the substrate. The drain electrode and the base region share a second common semiconductor region in the substrate. The body region and the collector region share a third common semiconductor region in the substrate.

Abstract: A semiconductor structure comprising an improved ESD protection device is provided. The semiconductor structure comprises a substrate, a well formed in the substrate, a first heavily doped region formed in the well, a second heavily doped region formed in the well and separated apart from the first heavily doped region, a gate structure formed on the substrate between the first heavily doped region and the second heavily doped region, a field region formed in the well under the first heavily doped region and the gate structure, and a field oxide/shallow trench isolation structure formed adjacent to the first heavily doped region. The field region is not formed under the second heavily doped region. The well and the field region have a first type of doping. The first heavily doped region and the second heavily doped region have a second type of doping.

Abstract: A semiconductor structure is provided. The semiconductor structure comprises: a substrate; a first doping region, a first well and a second doping region formed in the substrate; a plurality of first heavily doped regions formed in the first doping region; a plurality of conductors and a plurality of dielectrics formed on the substrate between the first heavily doped regions; a second heavily doped region formed in the first well; a third heavily doped region and a fourth heavily doped region formed in the second doping region; as well as a first gate electrode and a first gate dielectric. The first doping region, the first well, the second heavily doped region and the fourth heavily doped region have a first type of doping. The second doping region, the first heavily doped regions and the third heavily doped region have a second type of doping.

Abstract: A semiconductor element and a manufacturing method and an operating method of the same are provided. The semiconductor element includes a substrate, a first well, a first heavily doping region, at least a second heavily doping region, a gate layer, a third heavily doping region, and a fourth heavily doping region. The first well and the third heavily doping region are disposed on the substrate. The first and fourth heavily doping regions are disposed in the first well. The second heavily doping region is disposed in the first heavily doping region. The gate layer is disposed on the first well. The first, third, and fourth heavily doping regions having a first type doping are separated from one another. The first well and the second heavily doping region have a second type doping complementary to the first type doping.