Abstract: A disclosed semiconductor device includes a semiconductor deposition layer formed over an insulation structure and above a substrate. The device includes a gate formed over a contact region between first and second implant regions in the semiconductor deposition layer. The first and second implant regions both have a first conductivity type, and the gate has a second conductivity type. The device may further include a second gate formed beneath the semiconductor deposition layer.

Abstract: A bipolar junction transistor and an operating method and a manufacturing method for the same are provided. The bipolar junction transistor comprises a first doped region, a second doped region and a third doped region. The first doped region has a first type conductivity. The second doped region comprises well regions formed in the first doped region, having a second type conductivity opposite to the first type conductivity, and separated from each other by the first doped region. The third doped region has the first type conductivity. The third doped region is formed in the well regions or in the first doped region between the well regions.

Abstract: A semiconductor device is provided having a dual dielectric layer structure defined by a thin dielectric layer adjacent to a thick dielectric layer. More particularly, a high voltage metal oxide semiconductor transistor having a dual gate oxide layer structure comprising a thin gate oxide layer adjacent to a thick oxide/thin oxide layer may be provided. Such structures may be used in extended drain metal oxide semiconductor field effect transmitters, laterally diffused metal oxide field effect transistors, or any high voltage metal oxide semiconductor transistor. Methods of fabricating an extended drain metal oxide semiconductor transistor device are also provided.

Abstract: A semiconductor element and a manufacturing method and an operating method of the same are provided. The semiconductor element includes a substrate, a first well, a first heavily doping region, at least a second heavily doping region, a gate layer, a third heavily doping region, and a fourth heavily doping region. The first well and the third heavily doping region are disposed on the substrate. The first and fourth heavily doping regions are disposed in the first well. The second heavily doping region is disposed in the first heavily doping region. The gate layer is disposed on the first well. The first, third, and fourth heavily doping regions having a first type doping are separated from one another. The first well and the second heavily doping region have a second type doping complementary to the first type doping.

Abstract: A semiconductor structure is proposed. A third well is formed between a first well and a second well. A first doped region and a second doped region are formed in a surface of the third well. A third doped region is formed between the first doped region and the second doped region. A fourth doped region is formed in a surface of the first well. A fifth doped region is formed in a surface of the second well. A first base region and a second base region are respectively formed in surfaces of the first well and the second well. A first Schottky barrier is overlaid on a part of the first base region and the first doped region. A second Schottky barrier is overlaid on a part of the second base region and the second doped region.

Abstract: A semiconductor structure comprising a substrate, an active device, a field oxide layer and a poly-silicon resistor is disclosed. The active device is formed in a surface area of the substrate. The active device has a first doped area, a second doped area and a third doped area. The second doped area is disposed on the first doped area. The first doped area is between the second and the third doped areas. The first doped area has a first type conductivity. The third doped area has a second type conductivity. The first and the second type conductivities are different. The field oxide layer is disposed on a part of the third doped area. The poly-silicon resistor is disposed on the field oxide layer and is electrically connected to the third doped area.

Abstract: A semiconductor structure comprising a substrate, an active device, a field oxide layer and a poly-silicon resistor is disclosed. The active device is formed in a surface area of the substrate. The active device has a first doped area, a second doped area and a third doped area. The second doped area is disposed on the first doped area. The first doped area is between the second and the third doped areas. The first doped area has a first type conductivity. The third doped area has a second type conductivity. The first and the second type conductivities are different. The field oxide layer is disposed on a part of the third doped area. The poly-silicon resistor is disposed on the field oxide layer and is electrically connected to the third doped area.

Abstract: A semiconductor device comprising a high-voltage (HV) n-type metal oxide semiconductor (NMOS) embedded HV junction gate field-effect transistor (JFET) is provided. An HV NMOS with embedded HV JFET may include, according to a first example embodiment, a substrate, an N-type well region disposed adjacent to the substrate, a P-type well region disposed adjacent to the N-type well region, and first and second N+ doped regions disposed adjacent to the N-type well and on opposing sides of the P-type well region. The P-type well region may comprise a P+ doped region, a third N+ doped region and a gate structure, the third N+ doped region being interposed between the P+ doped region and the gate structure.

Abstract: A semiconductor device comprising a high-voltage (HV) n-type metal oxide semiconductor (NMOS) embedded HV junction gate field-effect transistor (JFET) is provided. An HV NMOS with embedded HV JFET may include, according to a first example embodiment, a substrate, an N-type well region disposed adjacent to the substrate, a P-type well region disposed adjacent to the N-type well region, and first and second N+ doped regions disposed adjacent to the N-type well and on opposing sides of the P-type well region. The P-type well region may comprise a P+ doped region, a third N+ doped region and a gate structure, the third N+ doped region being interposed between the P+ doped region and the gate structure.

Abstract: A metal-oxide-semiconductor (MOS) device is disclosed. The MOS device includes a substrate of a first impurity type, a diffused region of a second impurity type in the substrate, a patterned first dielectric layer including a first dielectric portion over the diffused region, a patterned first conductive layer on the patterned first dielectric layer, the patterned first conductive layer including a first conductive portion on the first dielectric portion, a patterned second dielectric layer including a second dielectric portion that extends on a first portion of an upper surface of the first conductive portion and along a sidewall of the first conductive portion to the substrate; and a patterned second conductive layer on the patterned second dielectric layer, the patterned second conductive layer including a second conductive portion on the second dielectric portion.

Abstract: A semiconductor device and an operating method for the same are provided. The semiconductor structure comprises a first doped region, a second doped region, a third doped region, a fourth doped region and a first gate structure. The first doped region has a first type conductivity. The second doped region has a second type conductivity opposite to the first type conductivity. The first doped region is surrounded by the second doped region. The third doped region has the first type conductivity. The fourth doped region has the second type conductivity. The first gate structure is on the second doped region. The third doped region and the fourth doped region are in the second doped region and the first doped region on opposing sides of the first gate structure respectively.

Abstract: A semiconductor device, a manufacturing method thereof and an operating method thereof are provided. The semiconductor device includes a substrate, a first well, a second well, a first heavily doping region, a second heavily doping region, a third heavily doping region, and an electrode layer. The first and the second wells are disposed on the substrate. The first and the third heavily doping regions, which are separated from each other, are disposed in the first well, and the second heavily doping region is disposed in the second well. The electrode layer is disposed on the first well. Each of the second well, the first heavily doping region, and the second heavily doping region has a first type doping. Each of the substrate, the first well, and the third heavily doping region has a second type doping, which is complementary to the first type doping.

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a first doped region and a semiconductor region. The first doped region has a first type conductivity. The semiconductor region is in the first doped region. A source electrode and a drain electrode are respectively electrically connected to parts of the first doped region on opposite sides of the semiconductor region.

Abstract: A semiconductor structure and a manufacturing method for the same are provided. The semiconductor structure includes a well region, a dielectric structure, a first doped layer, a second doped layer and a first doped region. The dielectric structure is on the well region. The dielectric structure has a first dielectric sidewall and a second dielectric sidewall opposite to each other. The dielectric structure includes a first dielectric portion and a second dielectric portion, between the first dielectric sidewall and the second dielectric sidewall. The first doped layer is on the well region between the first dielectric portion and the second dielectric portion. The second doped layer is on the first doped layer. The first doped region is in the well region on the first dielectric sidewall.

Abstract: A semiconductor structure and manufacturing method for the same, and an ESD circuit are provided. The semiconductor structure comprises a first doped region, a second doped region, a third doped region and a resistor. The first doped region has a first type conductivity. The second doped region has a second type conductivity opposite to the first type conductivity. The third doped region has the first type conductivity. The first doped region and the third doped region are separated by the second doped region. The resistor is coupled between the second doped region and the third doped region. An anode is coupled to the first doped region. A cathode is coupled to the third doped region.

Abstract: A metal-oxide-semiconductor (MOS) device is disclosed. The MOS device includes a substrate of a first impurity type, a diffused region of a second impurity type in the substrate, a patterned first dielectric layer including a first dielectric portion over the diffused region, a patterned first conductive layer on the patterned first dielectric layer, the patterned first conductive layer including a first conductive portion on the first dielectric portion, a patterned second dielectric layer including a second dielectric portion that extends on a first portion of an upper surface of the first conductive portion and along a sidewall of the first conductive portion to the substrate; and a patterned second conductive layer on the patterned second dielectric layer, the patterned second conductive layer including a second conductive portion on the second dielectric portion.

Abstract: A high voltage junction field effect transistor and a manufacturing method thereof are provided. The high voltage junction field effect transistor includes a base, a drain, a source and a P type top layer. The drain and the source are disposed above the base. A channel is formed between the source and the drain. The P type top layer is disposed above the channel.

Abstract: A semiconductor element, a manufacturing method thereof and an operating method thereof are provided. The semiconductor element includes a substrate, a first well, a second well, a third well, a fourth well, a bottom layer, a first heavily doping region, a second heavily doping region, a third heavily doping region and a field plane. The first well, the bottom layer and the second well surround the third well for floating the third well and the substrate. The first, the second and the third heavily doping regions are disposed in the first, the second and the third wells respectively. The field plate is disposed above a junction between the first well and the fourth well.

Abstract: A semiconductor device includes a source region, a drain region, and a drift region between the source and drain regions. A split gate is disposed over a portion of the drift region, and between the source and drain regions. The split gate includes first and second gate electrodes separated by a gate oxide layer. A self-aligned RESURF region is disposed within the drift region between the gate and the drain region. PI gate structures including an upper polysilicon layer are disposed near the drain region, such that the upper polysilicon layer can serve as a hard mask for the formation of the double RESURF structure, thereby allowing for self-alignment of the double RESURF structure.

Abstract: A semiconductor structure comprising a substrate, an active device, a field oxide layer and a poly-silicon resistor is disclosed. The active device is formed in a surface area of the substrate. The active device has a first doped area, a second doped area and a third doped area. The second doped area is disposed on the first doped area. The first doped area is between the second and the third doped areas. The first doped area has a first type conductivity. The third doped area has a second type conductivity. The first and the second type conductivities are different. The field oxide layer is disposed on a part of the third doped area. The poly-silicon resistor is disposed on the field oxide layer and is electrically connected to the third doped area.