Abstract: Provided is a semiconductor device including a metal oxide semiconductor transistor, a Zener diode, and a resistor. The metal oxide semiconductor transistor includes a gate, a source and a drain. The resistor has one end electrically connected to the drain, wherein the resistor includes a high resistance which is sufficient for flowing most of current to pass the metal oxide semiconductor transistor. The Zener diode includes a cathode and an anode, in which the cathode is electrically connected the gate and another end of the resistor, and the anode is electrically connected to a gate body.

Abstract: A semiconductor device including metal-on-semiconductor (MOS) and bipolar junction (BJ) structures formed in a substrate. The MOS structure includes a first region, a second region formed over the first region, a third region, and a fourth region formed over the third region. The first, second, and fourth regions have a first-type conductivity, being drain region, drain electrode, and source region of the MOS structure. Doping level of the second region is higher than that of the first region. The third region has a second-type conductivity, including channel and body regions of the MOS structure. The channel region is formed between the first and fourth regions. The BJ structure includes a fifth region formed over the first region, contacting the second region, having the second-type conductivity, and being an emitter region of the BJ structure. The second and third regions are base and collector regions of the BJ structure.

Abstract: A semiconductor structure is provided. The semiconductor structure comprises: a substrate; a first doping region, a first well and a second doping region formed in the substrate; a plurality of first heavily doped regions formed in the first doping region; a plurality of conductors and a plurality of dielectrics formed on the substrate between the first heavily doped regions; a second heavily doped region formed in the first well; a third heavily doped region and a fourth heavily doped region formed in the second doping region; as well as a first gate electrode and a first gate dielectric. The first doping region, the first well, the second heavily doped region and the fourth heavily doped region have a first type of doping. The second doping region, the first heavily doped regions and the third heavily doped region have a second type of doping.

Abstract: A bipolar junction transistor and an operating method and a manufacturing method for the same are provided. The bipolar junction transistor comprises a first doped region, a second doped region and a third doped region. The first doped region has a first type conductivity. The second doped region comprises well regions formed in the first doped region, having a second type conductivity opposite to the first type conductivity, and separated from each other by the first doped region. The third doped region has the first type conductivity. The third doped region is formed in the well regions or in the first doped region between the well regions.

Abstract: A semiconductor device includes a substrate having a first conductivity type, a first heavily-doped region formed in the substrate and having the first conductivity type, a second heavily-doped region formed in the substrate and having the first conductivity type, and an embedded layer formed in the substrate and separated from the first and second heavily-doped regions. The embedded layer has a second conductivity type different from the first conductivity type. A portion of the embedded layer is beneath the first heavily-doped region. A third heavily-doped region is formed in the substrate, between the first and second heavily-doped regions, and contacting the embedded layer, and has the second conductivity type.

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure comprises a first semiconductor region, a second semiconductor region, a dielectric structure and a gate electrode layer. The first semiconductor region has a first type conductivity. The second semiconductor region has a second type conductivity opposite to the first type conductivity. The first semiconductor region is adjoined to the second semiconductor region. The dielectric structure is on the first semiconductor region and the second semiconductor region. The gate electrode layer is on the dielectric structure.

Abstract: A semiconductor structure comprising an improved ESD protection device is provided. The semiconductor structure comprises a substrate, a well formed in the substrate, a first heavily doped region formed in the well, a second heavily doped region formed in the well and separated apart from the first heavily doped region, a gate structure formed on the substrate between the first heavily doped region and the second heavily doped region, a field region formed in the well under the first heavily doped region and the gate structure, and a field oxide/shallow trench isolation structure formed adjacent to the first heavily doped region. The field region is not formed under the second heavily doped region. The well and the field region have a first type of doping. The first heavily doped region and the second heavily doped region have a second type of doping.

Abstract: A high voltage (HV) device and method for manufacturing the same are provided, at least comprising a substrate, an insulation formed on the substrate, a deep well formed in the insulation, an air layer formed in the insulation and disposed adjacent to the bottom surface of the deep well. A bottom surface of the deep well is spaced apart from the substrate. Also, the air layer, interposed between the deep well and the substrate, is spaced apart from the substrate. In one embodiment, an air layer further communicates with an atmosphere outside the HV device, which facilitates heat dissipation.

Abstract: A semiconductor device and a manufacturing method of the same are provided. The semiconductor device includes a substrate, a first doping region, a first well, a resistor element, and a first, a second, and a third heavily doping regions. The first well and the third heavily doping region are disposed in the first doping region, which is disposed on the substrate. The first heavily doping region and the second heavily doping region, which are separated from each other, are disposed in the first well. The second and the third heavily doping regions are electrically connected via the resistor element. Each of the substrate, the first well, and the second heavily doping region has a first type doping. Each of the first doping region, the first heavily doping region, and the third heavily doping region has a second type doping, complementary to the first type doping.

Abstract: A high voltage semiconductor device is provided, comprising a high voltage metal-oxide-semiconductor transistor (HVMOS), and a normally-on low voltage metal-oxide-semiconductor transistor (LVMOS) electrically connected to the HVMOS. The HVMOS has a first collector and a first emitter, and the LVMOS has a second collector and a second emitter, wherein the second collector of the LVMOS is electrically connected to the first emitter of the HVMOS. The LVMOS electrically connected to the HVMOS provides an electro-static discharge bipolar transistor (ESD BJT), such as a NPN-type ESD BJT.

Abstract: A semiconductor device, in particular, an extended drain metal oxide semiconductor (ED-MOS) device, defined by a doped shallow drain implant in a drift region. For example, an extend drain n-channel metal oxide semiconductor (ED-NMOS) device is defined by an n doped shallow drain (NDD) implant in the drift region. The device is also characterized by conductive layer separated from a substrate in part by a thin oxide layer and in another part by a thick/thin oxide layer. A method of fabricating a semiconductor device, in particular an ED-NMOS device, having a doped shallow drain implant of a drift region is also provided. A method is also provided for fabricating conductive layer disposed in part across a thin oxide layer and in another part across a thick/thin oxide layer.

Abstract: A semiconductor device includes high-voltage (HV) and low-voltage (LV) MOS's formed in a substrate. The HV MOS includes a first semiconductor region having a first-type conductivity and a first doping level, a second semiconductor region having the first-type conductivity and a second doping level lower than the first doping level, a third semiconductor region having a second-type conductivity, and a fourth semiconductor region having the first-type conductivity. The first, second, third, and fourth semiconductor regions are arranged along a first direction, and are drain, drift, channel, and source regions, respectively, of the HV MOS. The LV MOS includes the fourth semiconductor region, a fifth semiconductor region having the second-type conductivity, and a sixth semiconductor region having the first-type conductivity.

Abstract: A semiconductor structure and a method for manufacturing the same are disclosed. The semiconductor structure comprises a substrate, a first well formed in the substrate, a first heavily doped region formed in the first well, a second heavily doped region formed in the substrate and separated apart from the first well, a second well formed in the substrate and under the second heavily doped region, a gate dielectric formed on the substrate between the first heavily doped region and the second heavily doped region, and a gate electrode formed on the gate dielectric. The gate dielectric has a substantially uniform thickness across at least a portion extending from a side close to the second heavily doped region. The first well has a first type of doping. The first heavily doped region, the second heavily doped region and the second well have a second type of doping.

Abstract: A semiconductor device includes a substrate having a first conductivity type, a first heavily-doped region formed in the substrate and having the first conductivity type, a second heavily-doped region formed in the substrate and having the first conductivity type, and an embedded layer formed in the substrate and separated from the first and second heavily-doped regions. The embedded layer has a second conductivity type different from the first conductivity type. A portion of the embedded layer is beneath the first heavily-doped region. A third heavily-doped region is formed in the substrate, between the first and second heavily-doped regions, and contacting the embedded layer, and has the second conductivity type.

Abstract: A semiconductor structure and an electrostatic discharge protection circuit are disclosed. The semiconductor structure includes a device structure comprising a first well region, a second well region, a source, a drain, an extending doped region, and a gate structure. The second well region has conductivity type opposite to a conductivity type of the first well region. The drain has a conductivity type same as a conductivity type of the source. The source and the drain are formed in the first well region and the second well region respectively. The extending doped region is adjoined with drain and extended under the drain. The extending doped region has a conductivity type same as the conductivity type of the drain. The gate structure is on the first well region.

Abstract: A semiconductor structure and an electrostatic discharge protection circuit are disclosed. The semiconductor structure includes a device structure comprising a first well region, a second well region, a source, a drain, an extending doped region, and a gate structure. The second well region has conductivity type opposite to a conductivity type of the first well region. The drain has a conductivity type same as a conductivity type of the source. The source and the drain are formed in the first well region and the second well region respectively. The extending doped region is adjoined with drain and extended under the drain. The extending doped region has a conductivity type same as the conductivity type of the drain. The gate structure is on the first well region.

Abstract: A high voltage semiconductor device is provided, comprising a high voltage metal-oxide-semiconductor transistor (HVMOS), and a normally-on low voltage metal-oxide-semiconductor transistor (LVMOS) electrically connected to the HVMOS. The HVMOS has a first collector and a first emitter, and the LVMOS has a second collector and a second emitter, wherein the second collector of the LVMOS is electrically connected to the first emitter of the HVMOS. The LVMOS electrically connected to the HVMOS provides an electro-static discharge bipolar transistor (ESD BJT), such as a NPN-type ESD BJT.

Abstract: Provided is a semiconductor device including a metal oxide semiconductor transistor, a Zener diode, and a resistor. The metal oxide semiconductor transistor includes a gate, a source and a drain. The resistor has one end electrically connected to the drain, wherein the resistor includes a high resistance which is sufficient for flowing most of current to pass the metal oxide semiconductor transistor. The Zener diode includes a cathode and an anode, in which the cathode is electrically connected the gate and another end of the resistor, and the anode is electrically connected to a gate body.

Abstract: Provided is a semiconductor device including a deep doped region of a first conductivity type, a well region of a second conductivity type, a base region of the first conductivity type, an insulated gate bipolar transistor (IGBT) and a metal oxide semiconductor (MOS). The well region is disposed in the deep doped region. The base region is disposed in the well region and is not connected to the deep doped region. The IGBT is disposed on the well region at the first side of the base region, and includes a first doped region of the second conductivity type disposed in the base region. The MOS is disposed on the well region and the deep well region at the second side of the base region, and includes a second doped region of the second conductivity type disposed in the base region.

Abstract: A semiconductor device and a manufacturing method for the same are provided. The semiconductor substrate includes a gate structure, a first doped contact region, a second doped contact region and a well doped region. The gate structure is on the semiconductor substrate, and has a first gate sidewall and a second gate sidewall opposite to the first gate sidewall. The first doped contact region has a first type conductivity and is formed in the semiconductor substrate on the first gate sidewall of the gate structure. The second doped contact region has the first type conductivity and is formed in the semiconductor substrate on the second gate sidewall of the gate structure. The well doped region has the first type conductivity and is under the first doped contact region.