Abstract: A cell of a resistive random access memory including (i) a resistive element and (ii) a switch. The resistive element includes (i) a first electrode, and (ii) a second electrode. The switch includes (i) a first terminal connected to a first contact, and (i) a second terminal connected to a second contact. The second contact is connected to the second electrode of the resistive element via a third contact. The third contact has a shape including a first surface and a second surface that is opposite to the first surface. The shape of the third contact tapers inward from the first surface towards the second surface.

Abstract: A resistive element of a resistive memory cell. The resistive element includes a contact in communication with a substrate. A bottom electrode is formed on the contact. A transitional metal oxide layer is formed on the bottom electrode. The transitional metal oxide layer includes oxygen vacancies configured to receive donor oxygen atoms. A transition layer formed on the transitional metal oxide layer includes donor oxygen atoms. A reactive metal layer is formed on the transition layer. A top electrode is formed on the transitional metal oxide layer. The transition layer is configured to provide the donor oxygen atoms to the transitional metal oxide layer in response to a voltage being applied to the top electrode.

Abstract: A memory system includes first memory cells and second memory cells. Each of the first memory cells includes first and second pass gates including NMOS transistors. Each of the second memory cells include first and second pass gates including PMOS transistors. The first memory cells are pre-charged by one polarity of a voltage supply. The second memory cells are pre-charged by an opposite polarity of the voltage supply.

Abstract: A memory including a memory cell and first and second modules. The memory cell has first and second states, where the second state is different than the first state. The first module, subsequent to an initial forming of the memory cell and subsequent to a read cycle or a write cycle of the memory cell, determines a first difference between the first state and a first predetermined threshold or a second difference between the first state and the second state. The second module, subsequent to the first module determining the first difference or the second difference, reforms the memory cell to reset and increase the first difference or the second difference. The second module, during the reforming of the memory cell, applies a first voltage to the memory cell. The first voltage is greater than a voltage applied to the memory cell during the read cycle or the write cycle.

Abstract: A method including: forming a stack of resistive layers; prior to or subsequent to forming the stack of resistive layers, forming a conductive layer; applying a mask layer on the stack of resistive layers or the conductive layer; forming a first spacer on the mask layer; and etching away a first portion of the mask layer using the first spacer as a first mask to provide a remainder. The method further includes: forming a second spacer on the stack of the resistive layers or the conductive layer and the remainder of the mask layer; etching away a second portion of the remainder of the mask layer to form an island; and using the island as a second mask, etching the stack of the resistive layers to form a resistive element of a memory, and etching the conductive layer to form a conductive element of the memory.

Abstract: The present disclosure describes techniques and apparatuses for multiport memory architecture. In some aspects serial data is received from a data port and converted to n-bit-wide words of data. The n-bit-wide words of data are then buffered as a k-word-long block of parallel data into a line of a multiline buffer as a block of k*n bits of data. The block of k*n bits of data is then transmitted to a multiport memory via a write bus effective to write the block of k*n bits of data to the multiport memory.

Abstract: Embodiments include a method comprising: receiving a first voltage; and while testing a memory cell: modifying the first voltage to generate a second voltage that is different from the first voltage; and performing a first read operation on the memory cell, based on applying (i) the second voltage to an array of transistors of the memory cell and (ii) the first voltage to the memory cell.

Abstract: A system including first and second devices. The first device generates a trigger signal to test a memory. The memory has memory cells including first and second cells. The first and second cells are defective and are in a same row or column. The second device: tests the memory in response to the trigger signal and based on a first frequency; generates an error signal in response to detecting the first cell as defective; and based on the test, generates information including first and second addresses of the first and second cells. The first device, based on the error signal, receives the information at a second frequency. The second device compares the first and second addresses, and if a match, continues the test without reporting the second cell as defective. The first device, based on a number of times the first address is matched, repairs the row or the column.

Abstract: A system including a resistive random access memory cell connected to a word line and a bit line and a pre-charge circuit configured to pre-charge the bit line to a first voltage with the word line being unselected. A driver circuit selects the word line at a first time subsequent to the bit line being charged to the first voltage. A comparator compares a second voltage on the bit line to a third voltage supplied to the comparator and generates an output based on the comparison. A latch latches the output of the comparator and generates a latched output. A pulse generator generates a pulse after a delay subsequent to the first time to clock the latch to latch the output of the comparator and generate the latched output. The latched output indicates a state of the resistive random access memory cell.

Abstract: A system includes a resistive random access memory cell and a driver circuit. The resistive random access memory cell includes a resistive element and a switching element, and has a first terminal connected to a bit line and a second terminal connected to a word line. The driver circuit is configured to apply, in response to selection of the resistive random access memory cell using the word line, a first voltage of a first polarity to the bit line to program the resistive random access memory cell to a first state by causing current to flow through the resistive element in a first direction, and a second voltage of a second polarity to the bit line to program the resistive random access memory cell to a second state by causing current to flow through the resistive element in a second direction.

Abstract: A static random access memory (SRAM) cell includes first and second n-channel transistors, first and second p-channel transistors, first and second enable transistors, and first and second pass gates. The first n-channel transistor, the first p-channel transistor, and the first enable transistor are connected in series between first and second reference potentials. The second n-channel transistor, the second p-channel transistor, and the second enable transistor are connected in series between the first and second reference potentials. The first pass gate is configured to selectively connect a first bitline to a first node. The first node is connected to a gate of the first n-channel transistor and a gate of the first p-channel transistor. The second pass gate is configured to selectively connect a second bitline to a second node. The second node is connected to a gate of the second n-channel transistor and a gate of the second p-channel transistor.

Abstract: A cell of a resistive random access memory including (i) a resistive element and (ii) a switch. The resistive element includes (i) a first electrode, and (ii) a second electrode. The switch includes (i) a first terminal connected to a first contact, and (i) a second terminal connected to a second contact. The second contact is connected to the second electrode of the resistive element via a third contact. The third contact has a shape including a first surface and a second surface that is opposite to the first surface. The shape of the third contact tapers inward from the first surface towards the second surface.

Abstract: Methods and structures for transistors having reduced source contact to gate spacings in semiconductor devices are disclosed. In one embodiment, a method of forming a transistor can include: forming a gate over an active area of the transistor; forming source and drain regions aligned to the gate in the active area; forming source and drain contacts over the source and drain regions, where a spacing from the gate to the source contact of the transistor is less than a spacing from the gate to the drain contact of the transistor; and using one or more modified masks for forming doping profiles for the source region and the drain region.

Abstract: A memory including a memory cell and first and second modules. The memory cell has first and second states, where the second state is different than the first state. The first module, subsequent to an initial forming of the memory cell and subsequent to a read cycle or a write cycle of the memory cell, determines a first difference between the first state and a first predetermined threshold or a second difference between the first state and the second state. The second module, subsequent to the first module determining the first difference or the second difference, reforms the memory cell to reset and increase the first difference or the second difference. The second module, during the reforming of the memory cell, applies a first voltage to the memory cell. The first voltage is greater than a voltage applied to the memory cell during the read cycle or the write cycle.

Abstract: A resistive memory having a plurality of resistive elements, each having a resistance that changes with respect to a state of the resistive memory element. The resistive memory includes a substrate, a first memory access device formed on the substrate, a first contact formed on the first memory access device, and a first resistive memory element formed on the first contact. The first resistive memory element has a first polarity. The first memory access device provides read and write access to the state of the first resistive memory element. A second memory access device is formed on the substrate, a second contact formed on the second memory access device, and a second resistive memory element formed on the second contact. The second resistive memory element has a second polarity. The second memory access device provides read and write access to the state of the second resistive memory element.

Abstract: In one embodiment, the present disclosure includes a circuit comprising an amplifier having an input and an output, an offset detection circuit to detect an offset of the amplifier at the output of the amplifier, and an offset generation circuit having an input coupled to the offset detection circuit and an output coupled to the input of the amplifier to generate an offset at the input of the amplifier during an operational phase of the amplifier based on the detected offset. The generated offset cancels a least a portion of the offset of the amplifier. In one implementation, the amplifier is a sense amplifier in a memory.

Abstract: A cell of a resistive random access memory including a resistive element and an access device. The resistive element includes (i) a first electrode and (ii) a second electrode. The access device is configured to select and deselect the cell. The access device includes (i) a first terminal connected to a first contact and (i) a second terminal connected to a second contact. The second contact is connected to the second electrode of the resistive element via a third contact. The third contact includes (i) a first surface in contact with the second contact and (ii) a second surface in contact with the second electrode. The first surface defines a first surface area, and the second surface defines a second surface area. The first surface area is greater than the second surface area.

Abstract: A memory system includes a memory array and a read/write module. The memory array includes bit lines, word lines, and memory cells. Each of the memory cells is located at an intersection of a respective one of the bit lines and a respective one of the word lines. The memory cells include a first memory cell and a second memory cell. The first memory cell is located at the intersection of a first bit line of the bit lines and a first word line of the word lines. The second memory cell is located at the intersection of a second bit line of the bit lines and a second word line of the word lines. The read/write module is configured to concurrently activate the first memory cell and the second memory cell to simultaneously access both the first memory cell and the second memory cell.

Abstract: A memory includes an array of memory cells, a first module and a second module. The first module is configured to compare a first state of a memory cell with a reference. The memory cell is in the array of memory cells. The second module is configured to, subsequent to a read cycle or a write cycle of the memory cell and based on the comparison, reform the memory cell to adjust a difference between the first state and a second state of the memory cell.

Abstract: A memory includes a module and a demultiplexer. The module is configured to monitor outputs of sense amplifiers. Each of the outputs of the sense amplifiers is configured to be in a first state or a second state. The module is configured to determine that two or more of the outputs of the sense amplifiers are in a same state. The same state is the first state or the second state. The module is configured to output the state of the two or more outputs of the sense amplifiers. The demultiplexer is configured to provide the state of the two or more outputs of the sense amplifiers to a latch.