Abstract: A radial memory device includes a phase-change material, a first electrode in electrical communication with the phase-change material, the first electrode having a first area of electrical communication with the phase-change material. A second electrode in electrical communication with the phase-change material, the second electrode having a second area of electrical communication with the phase-change material, and the second area being laterally spacedly disposed from the first area. Additionally, the radial memory device includes a dielectric layer disposed between the first electrode and the second electrode, the dielectric layer having an opening therethrough, the phase-change material being disposed in the opening, wherein the phase-change material is disposed at least partially above the second electrode. Further, a method of making a memory device is disclosed.

Abstract: A radial memory device includes a phase-change material, a first electrode in electrical communication with the phase-change material, the first electrode having a substantially planar first area of electrical communication with the phase-change material. The radial memory device also includes a second electrode in electrical communication with the phase-change material, the second electrode having a second area of electrical communication with the phase-change material, the second area being laterally spacedly disposed from the first area and substantially circumscribing the first area. Further, a method of making a memory device is disclosed. The steps include depositing a first electrode, depositing a first insulator, configuring the first insulator to define a first opening. The first opening provides for a generally planar first contact of the first electrode.

Abstract: A multi-layer chalcogenide electronic device. The device includes an active region in electrical communication with two terminals, where the active region includes two or more layers. In one embodiment, the pore region includes two or more chalcogenide materials which differ in chemical composition. In another embodiment, the pore region includes one or more chalcogenide materials and a layer of Sb. The devices offer the advantages of minimal conditioning requirements, fast set speeds, high reset resistances and low set resistances.

Abstract: A chalcogenide material and chalcogenide memory device having less stringent requirements for formation, improved thermal stability and/or faster operation. The chalcogenide materials include materials comprising Ge, Sb and Te in which the Ge and/or Te content is lean relative to the commonly used Ge2Sb2Te5 chalcogenide composition. Electrical devices containing the instant chalcogenide materials show a rapid convergence of the set resistance during cycles of setting and resetting the device from its as-fabricated state, thus leading to a reduced or eliminated need to subject the device to post-fabrication electrical formation prior to end-use operation. Improved thermal stability is manifested in terms of prolonged stability of the resistance of the device at elevated temperatures, which leads to an inhibition of thermally induced setting of the reset state in the device. Significant improvements in the 10 year data retention temperature are demonstrated.

Abstract: A chalcogenide material and chalcogenide memory device exhibiting fast operation (short set pulse times) over an extended range of reset state resistances. Electrical devices containing the instant chalcogenide materials permit rapid transformations from the reset state to the set state for reset and set states having a high resistance ratio. The instant devices thus provide for high resistance contrast and improved readability of memory states while preserving fast operational speeds for the device. The chalcogenide materials include materials comprising Ge, Sb and Te in which the Ge and/or Te content is lean relative to the commonly used Ge2Sb2Te5 chalcogenide composition. In one embodiment, the atomic concentration of Ge is between 11% and 22%, the atomic concentration of Sb is between 22% and 65%, and the atomic concentration of Te is between 28% and 55%.

Abstract: A phase change memory may be read so as to reduce the likelihood of a read disturb. A read disturb may occur, for example, when a reset device is raised to a voltage, which causes its threshold device to trigger. The triggering of the threshold device produces a displacement current which may convert a reset device to a set device. By ensuring that the reset cell never reaches a voltage that would result in triggering of the threshold device, read disturbs may be reduced.

Abstract: A carbon containing layer may be formed between a pair of chalcogenide containing layers of a phase change memory. When the lower chalcogenide layer allows current to pass, a filament may be formed therein. The filament then localizes the electrical heating of the carbon containing layer, converting a relatively localized region to a lower conductivity region. This region then causes the localization of heating and current flow through the upper phase change material layer. In some embodiments, less phase change material may be required to change phase to form a phase change memory, reducing the current requirements of the resulting phase change memory.

Abstract: A phase change memory may transition between two crystalline states. In one embodiment, the phase change material is a chalcogenide which transitions between face centered cubic and hexagonal states. Because these states are more stable, they are less prone to drift than the amorphous state conventionally utilized in phase change memories.

Abstract: A programmable resistance memory element comprising a dielectric material between a programmable resistance memory material and a threshold switching material.

Abstract: A method of making an electrically programmable memory element, comprising: providing a conductive sidewall spacer; and forming a phase-change material in electrical communication with said conductive sidewall spacer.

Abstract: A method of testing a programmable resistance memory element. The method comprises applying a plurality of reset pulses to the memory element. Each of the reset pulses having an energy which is greater than the minimum energy needed program the memory element from its set state to its reset state.

Abstract: A programmable resistance memory element comprising a dielectric material between a programmable resistance memory material and a threshold switching material.

Abstract: A memory element comprising a volume of phase change memory material; and first and second contact for supplying an electrical signal to the memory material, wherein the first contact comprises a conductive sidewall spacer. Alternately, the first contact may comprise a contact layer having an edge adjacent to the memory material.

Abstract: A method of operating a electrically programmable phase-change memory element. The method includes the step of applying an electrical signal to memory element which is sufficient to return the memory element to its pre-drift resistance state.

Abstract: A programmable resistance memory element comprising a dielectric material between a programmable resistance memory material and a threshold switching material.

Abstract: A programmable resistance memory element comprising alternating layers of programmable resistance material layers and stabilizing layers. The stabilizing layers may include metallic titanium or a titanium alloy. The stabilizing layers may include a telluride, such as titanium telluride.

Abstract: A method of making an electrically programmable memory element, comprising: providing a first dielectric layer; forming a conductive material over the first dielectric layer; forming a second dielectric layer over the conductive material; and forming a programmable resistance material in electrical contact with a peripheral surface of the conductive material.

Abstract: A method of operating a electrically programmable phase-change memory element. The method includes the step of applying an electrical signal to memory element which is sufficient to return the memory element to its pre-drift resistance state.

Abstract: A programmable resistance memory element comprising alternating layers of programmable resistance material layers and stabilizing layers. The stabilizing layers may include metallic titanium or a titanium alloy. The stabilizing layers may include a telluride, such as titanium telluride.

Abstract: A memory device including a plurality of memory cells, a plurality of insulated first regions of a first type of conductivity formed in a chip of semiconductor material, at least one second region of a second type of conductivity formed in each first region, a junction between each second region and the corresponding first region defining a unidirectional conduction access element for selecting a corresponding memory cell connected to the second region when forward biased, and at least one contact for contacting each first region; a plurality of access elements are formed in each first region, the access elements being grouped into at least one sub-set consisting of a plurality of adjacent access elements without interposition of any contact, and the memory device further includes means for forward biasing the access elements of each sub-set simultaneously.