Abstract: The present invention relates to a method for preparing an alkali metal ion conductive chalcogenide-based solid electrolyte, a solid electrolyte prepared thereby, and an all-solid-state battery comprising the same.

Abstract: A display device includes a substrate including a display area and a non-display area, a plurality of pixels disposed in the display area, a common voltage supply wiring overlapping the non-display area and disposed on the substrate, a driving voltage supply wiring overlapping the non-display area and disposed on the substrate, and a data voltage supply wiring overlapping the non-display area and electrically connected to the plurality of pixels, where at least one of the common voltage supply wiring and the driving voltage supply wiring includes a chamfered area, the data voltage supply wiring includes a first data voltage supply wiring, a second data voltage supply wiring, and a third data voltage supply wiring, and the first to third data voltage supply wirings are disposed in different layers.

Abstract: Devices and methods include transmitting loopback signals for monitoring operation of a memory device. In some embodiments, a memory device may receive a system clock signal from a host device and may generate an internal clock signal based at least in part on the system clock signal. In some embodiments, the memory device may generate a loopback signal based at least in part on the internal clock signal and may transmit the loopback signal via a loopback datapath associated with the memory device. A host device may compare the internal clock signal and the system clock signal to determine a fidelity of the internal clock signal. Termination values of the memory device may be adjusted based on the determined fidelity of the internal clock signal.

Abstract: The present disclosure relates to a sub-nanometric particles-metal organic framework complex including a multi-shell hollow metal organic framework (MOF) and sub-nanometric particles (SNPs), and a method of preparing the same.

Abstract: An innovative low-bit-width device may include a first digital-to-analog converter (DAC), a second DAC, a plurality of non-volatile memory (NVM) weight arrays, one or more analog-to-digital converters (ADCs), and a neural circuit. The first DAC is configured to convert a digital input signal into an analog input signal. The second DAC is configured to convert a digital previous hidden state (PHS) signal into an analog PHS signal. NVM weight arrays are configured to compute vector matrix multiplication (VMM) arrays based on the analog input signal and the analog PHS signal. The NVM weight arrays are coupled to the first DAC and the second DAC. The one or more ADCs are coupled to the plurality of NVM weight arrays and are configured to convert the VMM arrays into digital VMM values. The neural circuit is configured to process the digital VMM values into a new hidden state.

Abstract: Certain aspects of the present disclosure provide a method for performing multimode inferencing, comprising: receiving machine learning model input data from a requestor; processing the machine learning model input data with a machine learning model using processing hardware at a first power level to generate first output data; selecting a second power level for the processing hardware based on comparing the first output data to a threshold value; processing the machine learning model input data with the machine learning model using the processing hardware at the second power level to generate second output data; and sending second output data to the requestor.

Abstract: Methods and systems for testing memory systems are disclosed. A refresh rate for a test system including a number of memory devices may be controlled based on estimated power scenario of a memory system design. In response to performance of a number of refresh operations on the memory devices and based on the refresh rate, one or more conditions of the test system may be monitored to generate estimated performance data for the memory system design.

Abstract: An anti-icing honeycomb core composite manufactured by forming an electromagnetic wave absorption layer by using dielectric fiber, molding the electromagnetic wave absorption layer into a honeycomb core structure by using a molded part including a first base, a second base, and an inner block, hardening the honeycomb core structure, and removing the molded part. The molding step includes first stacking, on the first base including a plurality of grooves in which the inner blocks each having a hexagonal column shape are able to be seated, a plurality of the inner blocks and a plurality of the electromagnetic wave absorption layers as the honeycomb core structure so that the electromagnetic wave absorption layer is disposed between the plurality of inner blocks, and second stacking covering the inner blocks and the electromagnetic wave absorption layers stacked on the first base with the second base having the same shape as the first base.

Abstract: Non-volatile memory structures for performing compute in memory inferencing for neural networks are presented. To improve performance, both in terms of speed and energy consumption, weight matrices are replaced with their singular value decomposition (SVD) and use of a low rank approximations (LRAs). The decomposition matrices can be stored in a single array, with the resultant LRA matrices requiring fewer weight values to be stored. The reduced sizes of the LRA matrices allow for inferencing to be performed more quickly and with less power. In a high performance and energy efficiency mode, a reduced rank for the SVD matrices stored on a memory die is determined and used to increase performance and reduce power needed for an inferencing operation.

Abstract: Methods and apparatus are disclosed for implementing principal component analysis (PCA) within a non-volatile memory (NVM) die of solid state drive (SSD) to reduce the dimensionality of machine learning data before the data is transferred to other components of the SSD, such as to a data storage controller equipped with a machine learning engine. The machine learning data may include, for example, training images for training an image recognition system in which the SSD is installed. In some examples, the on-chip PCA components of the NVM die are configured as under-the-array or next-to-the-array components. In other examples, one or more arrays of the NVM die are configured as multiplication cores for performing PCA matrix multiplication. In still other aspects, multiple NVM dies are arranged in parallel, each with on-chip PCA components to permit parallel concurrent on-chip processing of machine learning data.

Abstract: Techniques are presented for performing in-memory matrix multiplication operations for binary input, binary weight valued convolution neural network (CNN) inferencing. The weights of a filter are stored in pairs of memory cells of a storage class memory device, such as a ReRAM or phase change memory based devices. To reduce current consumption, the binary valued filters are transformed into ternary valued filters by taking sums and differences of binary valued filter pairs. The zero valued weights of the transformed filters are stored as a pair of high resistance state memory cells, reducing current consumption during convolution. The results of the in-memory multiplications are pair-wise combined to compensate for the filter transformations. To compensate for zero valued weights, a zero weight register stores the number of zero weights along each bit line and is used to initialize counter values for accumulating the multiplication operations.

Abstract: Use of a NAND array architecture to realize a binary neural network (BNN) allows for matrix multiplication and accumulation to be performed within the memory array. A unit synapse for storing a weight of a BNN is stored in a pair of series connected memory cells. A binary input is applied on a pair of word lines connected to the unit synapse to perform the multiplication of the input with the weight. The results of such multiplications are determined by a sense amplifier, with the results accumulated by a counter. The arrangement extends to ternary inputs to realize a ternary-binary network (TBN) by adding a circuit to detect 0 input values and adjust the accumulated count accordingly. The arrangement further extends to a ternary-ternary network (TTN) by allowing 0 weight values in a unit synapse, maintaining the number of 0 weights in a register, and adjusting the count accordingly.

Abstract: Disclosed is a method for automatically replacing high-pressure gas barrels, in which when loading a high-pressure gas barrel is loaded on the lift of a cabinet so as to supply gas to the wafer production line in the semiconductor fabrication FAB process facility, at the time point of replacement of the high-pressure gas barrel, a used high-pressure gas barrel is separated from a connector holder and then a new high-pressure gas barrel is connected to the connector holder.

Abstract: A method for automatically opening or closing a gas barrel valve, includes: loading and aligning a gas barrel in a cabinet; separating an end cap from the gas barrel; screw-coupling a connector holder to a gas spray nozzle, from which the ends cap has been removed; winding a spring around a first shaft by enabling forward rotation of the first shaft while suppressing reverse rotation of the first shaft, which is installed in a valve handle holder so as to idle; opening a valve by enabling reverse rotation of a valve handle of the gas barrel while preventing forward rotation of the valve handle holder; and automatically closing the valve at the time of replacement of the gas barrel or when a gas leak is detected.

Abstract: Methods and systems for testing memory systems are disclosed. A refresh rate for a test system including a number of memory devices may be controlled based on estimated power scenario of a memory system design. In response to performance of a number of refresh operations on the memory devices and based on the refresh rate, one or more conditions of the test system may be monitored to generate estimated performance data for the memory system design.

Abstract: Techniques are presented for accelerating in-memory matrix multiplication operations for a convolution neural network (CNN) inference in which the weights of a filter are stored in the memory of a storage class memory device, such as a ReRAM or phase change memory based device. To improve performance for inference operations when filters exhibit sparsity, a zero column index and a zero row index are introduced to account for columns and rows having all zero weight values. These indices can be saved in a register on the memory device and when performing a column/row oriented matrix multiplication, if the zero row/column index indicates that the column/row contains all zero weights, the access of the corresponding bit/word line is skipped as the result will be zero regardless of the input.

Abstract: Methods, systems, and devices for initializing memory systems are described. A memory system may transmit, to a host system over a first channel, signaling indicative of a first set of values for a set of parameters associated with communicating information over a second channel between a storage device of the memory system and a memory device of the memory system. The host system may transmit, to the memory system, additional signaling associated with the first set of values for the set of parameters. For instance, the host system may transmit a second set of values for the set of parameters, an acknowledgement to use the first set of values, or a command to perform a training operation on the second channel to identify a second set of values for the set of parameters. The memory system may communicate the information over the second channel based on the additional signaling.

Abstract: Systems and methods for reducing the impact of defects within a crossbar memory array when performing multiplication operations in which multiple control lines are concurrently selected are described. A group of memory cells within the crossbar memory array may be controlled by a local word line that is controlled by a local word line gating unit that may be configured to prevent the local word line from being biased to a selected word line voltage during an operation; the local word line may instead be set to a disabling voltage during the operation such that the memory cell currents through the group of memory cells are eliminated. If a defect has caused a short within one of the memory cells of the group of memory cells, then the local word line gating unit may be programmed to hold the local word line at the disabling voltage during multiplication operations.

Abstract: Technology for reconfigurable input precision in-memory computing is disclosed herein. Reconfigurable input precision allows the bit resolution of input data to be changed to meet the requirements of in-memory computing operations. Voltage sources (that may include DACs) provide voltages that represent input data to memory cell nodes. The resolution of the voltage sources may be reconfigured to change the precision of the input data. In one parallel mode, the number of DACs in a DAC node is used to configure the resolution. In one serial mode, the number of cycles over which a DAC provides voltages is used to configure the resolution. The memory system may include relatively low resolution voltage sources, which avoids the need to have complex high resolution voltage sources (e.g., high resolution DACs). Lower resolution voltage sources can take up less area and/or use less power than higher resolution voltage sources.

Abstract: A non-volatile memory device includes an array of non-volatile memory cells that are configured to store weights of a neural network. Associated with the array is a data latch structure that includes a page buffer, which can store weights for a layer of the neural network that is read out of the array, and a transfer buffer, that can store inputs for the neural network. The memory device can perform multiply and accumulate operations between inputs and weight of the neural network within the latch structure, avoiding the need to transfer data out of the array and associated latch structure for portions of an inference operation. By using binary weights and inputs, multiplication can be performed by bit-wise XNOR operations. The results can then be summed and activation applied, all within the latch structure.