Patents by Inventor Won-Ho Choi
Won-Ho Choi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10991414Abstract: A system and method for refreshing memory cells of a memory device includes storing each bit of a B-bit word in a different sub-array of a memory device. Each of the bits is associated with a bit position, and the memory device includes a plurality of sub-arrays. The system and method also include determining a refresh interval for a plurality of the bit positions based upon a relative importance of the plurality of the bit positions to a performance of a machine learning or signal processing task involving the B-bit word. The refresh interval is based upon a fidelity metric and a resource metric. The system and method further include refreshing the plurality of sub-arrays based upon the refresh interval determined for the plurality of bit positions, and dynamically updating the refresh interval for the plurality of bit positions upon receiving a new fidelity metric or a new resource metric.Type: GrantFiled: September 27, 2019Date of Patent: April 27, 2021Assignee: Western Digital Technologies, Inc.Inventors: Yongjune Kim, Won Ho Choi, Cyril Guyot, Yuval Cassuto
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Publication number: 20210117499Abstract: Systems and methods for reducing the impact of defects within a crossbar memory array when performing multiplication operations in which multiple control lines are concurrently selected are described. A group of memory cells within the crossbar memory array may be controlled by a local word line that is controlled by a local word line gating unit that may be configured to prevent the local word line from being biased to a selected word line voltage during an operation; the local word line may instead be set to a disabling voltage during the operation such that the memory cell currents through the group of memory cells are eliminated. If a defect has caused a short within one of the memory cells of the group of memory cells, then the local word line gating unit may be programmed to hold the local word line at the disabling voltage during multiplication operations.Type: ApplicationFiled: October 17, 2019Publication date: April 22, 2021Applicant: SanDisk Technologies LLCInventors: Minghai Qin, Pi-Feng Chiu, Wen Ma, Won Ho Choi
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Publication number: 20210117500Abstract: Systems and methods for reducing the impact of defects within a crossbar memory array when performing multiplication operations in which multiple control lines are concurrently selected are described. A group of memory cells within the crossbar memory array may be controlled by a local word line that is controlled by a local word line gating unit that may be configured to prevent the local word line from being biased to a selected word line voltage during an operation; the local word line may instead be set to a disabling voltage during the operation such that the memory cell currents through the group of memory cells are eliminated. If a defect has caused a short within one of the memory cells of the group of memory cells, then the local word line gating unit may be programmed to hold the local word line at the disabling voltage during multiplication operations.Type: ApplicationFiled: June 26, 2020Publication date: April 22, 2021Applicant: SanDisk Technologies LLCInventors: Minghai Qin, Pi-Feng Chiu, Wen Ma, Won Ho Choi
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Publication number: 20210110235Abstract: Techniques are presented for accelerating in-memory matrix multiplication operations for a convolution neural network (CNN) inference in which the weights of a filter are stored in the memory of a storage class memory device, such as a ReRAM or phase change memory based device. To improve performance for inference operations when filters exhibit sparsity, a zero column index and a zero row index are introduced to account for columns and rows having all zero weight values. These indices can be saved in a register on the memory device and when performing a column/row oriented matrix multiplication, if the zero row/column index indicates that the column/row contains all zero weights, the access of the corresponding bit/word line is skipped as the result will be zero regardless of the input.Type: ApplicationFiled: October 15, 2019Publication date: April 15, 2021Applicant: SanDisk Technologies LLCInventors: Tung Thanh Hoang, Won Ho Choi, Martin Lueker-Boden
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Publication number: 20210110244Abstract: Use of a NAND array architecture to realize a binary neural network (BNN) allows for matrix multiplication and accumulation to be performed within the memory array. A unit synapse for storing a weight of a BNN is stored in a pair of series connected memory cells. A binary input is applied on a pair of word lines connected to the unit synapse to perform the multiplication of the input with the weight. The results of such multiplications are determined by a sense amplifier, with the results accumulated by a counter. The arrangement extends to ternary inputs to realize a ternary-binary network (TBN) by adding a circuit to detect 0 input values and adjust the accumulated count accordingly. The arrangement further extends to a ternary-ternary network (TTN) by allowing 0 weight values in a unit synapse, maintaining the number of 0 weights in a register, and adjusting the count accordingly.Type: ApplicationFiled: October 15, 2019Publication date: April 15, 2021Applicant: SanDisk Technologies LLCInventors: Tung Thanh Hoang, Won Ho Choi, Martin Lueker-Boden
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Publication number: 20210098041Abstract: A system and method include determining, by a memory controller associated with a memory device, a value of a parameter of a write pulse for a plurality of bits of a B-bit word to be stored in the memory device. The value of the parameter is based upon a relative importance of a bit position of the plurality of bits in the B-bit word to a performance of a machine learning or signal processing task involving the B-bit word, a fidelity metric, and a resource metric. The system and method also include writing each of the plurality of bits of the B-bit word in a different sub-array of the memory device using the write pulse generated based on the value of the parameter determined for a particular one of the plurality of bits.Type: ApplicationFiled: September 27, 2019Publication date: April 1, 2021Applicant: Western Digital Technologies, Inc.Inventors: Yongjune Kim, Yoocharn Jeon, Won Ho Choi, Cyril Guyot, Yuval Cassuto
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Publication number: 20210083173Abstract: Apparatuses, systems, and methods are disclosed for magnetoresistive random access memory. A magnetic tunnel junction (MTJ) for storing data may include a reference layer. A free layer of an MTJ may be separated from a reference layer by a barrier layer. A free layer may be configured such that one or more resistance states for an MTJ correspond to one or more positions of a magnetic domain wall within the free layer. A domain stabilization layer may be coupled to a portion of a free layer, and may be configured to prevent migration of a domain wall into the portion of the free layer.Type: ApplicationFiled: December 2, 2020Publication date: March 18, 2021Applicant: SanDisk Technologies LLCInventors: Young-Suk Choi, Won Ho Choi
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Publication number: 20210080061Abstract: Disclosed is a high-pressure gas cylinder automatic replacement device, including: a holder fixedly provided on a main plate to be positioned at one side of a connector holder of a high-pressure gas cylinder connection unit; a movable member rotatably provided at the holder; a two-stage actuator provided at the holder such that rods thereof are respectively connected to the movable member and a bracket fixed to the main plate; a docking actuator enabling the movable member to move from the holder towards the connector holder side or vice versa; a gasket removal cartridge provided at the movable member to automatically remove used gaskets from the connector holder and to accommodate the same in turn; and a gasket insertion cartridge provided at the movable member positioned at the upper portion of the gasket removal cartridge to insert a new gasket accommodated therein into the connector holder.Type: ApplicationFiled: December 13, 2018Publication date: March 18, 2021Applicant: AMT CO., LTD.Inventor: Won Ho CHOI
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Patent number: 10886459Abstract: Apparatuses, systems, and methods are disclosed for magnetoresistive random access memory. A magnetic tunnel junction (MTJ) for storing data may include a reference layer. A free layer of an MTJ may be separated from a reference layer by a barrier layer. A free layer may be configured such that one or more resistance states for an MTJ correspond to one or more positions of a magnetic domain wall within the free layer. A domain stabilization layer may be coupled to a portion of a free layer, and may be configured to prevent migration of a domain wall into the portion of the free layer.Type: GrantFiled: June 24, 2019Date of Patent: January 5, 2021Assignee: SanDisk Technologies LLCInventors: Young-Suk Choi, Won Ho Choi
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Patent number: 10886458Abstract: Apparatuses, systems, and methods are disclosed for magnetoresistive random access memory. A magnetic tunnel junction for storing data may include a reference layer, a barrier layer, and a free layer. A barrier layer may be disposed between a reference layer and a free layer. A free layer may include a nucleation region and an arm. A nucleation region may be configured to form a magnetic domain wall. An arm may be narrower than a nucleation region and may extend from the nucleation region. An arm may include a plurality of pinning sites formed at predetermined locations along the arm for pinning a domain wall.Type: GrantFiled: June 24, 2019Date of Patent: January 5, 2021Assignee: SanDisk Technologies LLCInventors: Young-Suk Choi, Won Ho Choi
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Publication number: 20200411065Abstract: An illustrative embodiment disclosed herein is an apparatus including a non-volatile memory cell and multi-bit input circuitry that simultaneously receives a plurality of bits, receives a supply voltage, converts the plurality of bits and the supply voltage into a multiply voltage, and applies the multiply voltage to the non-volatile memory cell. The non-volatile memory cell may pass a memory cell current in response to the multiply voltage. A magnitude of the multiply voltage may represent a multiplier. The memory cell current may represent a product of the multiplier and a multiplicand stored in the non-volatile memory cell.Type: ApplicationFiled: July 2, 2019Publication date: December 31, 2020Applicant: SanDisk Technologies LLCInventors: Won Ho Choi, Pi-Feng Chiu, Martin Lueker-Boden
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Publication number: 20200411066Abstract: An illustrative embodiment disclosed herein is an apparatus including a non-volatile memory cell and multi-bit input circuitry that simultaneously receives a plurality of bits, receives a supply voltage, converts the plurality of bits and the supply voltage into a multiply voltage, and applies the multiply voltage to the non-volatile memory cell. The non-volatile memory cell may pass a memory cell current in response to the multiply voltage. A magnitude of the multiply voltage may represent a multiplier. The memory cell current may represent a product of the multiplier and a multiplicand stored in the non-volatile memory cell.Type: ApplicationFiled: June 12, 2020Publication date: December 31, 2020Applicant: SanDisk Technologies LLCInventors: Won Ho Choi, Pi-Feng Chiu, Martin Lueker-Boden
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Publication number: 20200410334Abstract: An illustrative embodiment disclosed herein is an apparatus including a non-volatile memory cell and multi-bit input circuitry that simultaneously receives a plurality of bits, receives a supply voltage, converts the plurality of bits and the supply voltage into a multiply voltage, and applies the multiply voltage to the non-volatile memory cell. The non-volatile memory cell may pass a memory cell current in response to the multiply voltage. A magnitude of the multiply voltage may represent a multiplier. The memory cell current may represent a product of the multiplier and a multiplicand stored in the non-volatile memory cell.Type: ApplicationFiled: June 25, 2019Publication date: December 31, 2020Applicant: SanDisk Technologies LLCInventors: Won Ho Choi, Pi-Feng Chiu, Martin Lueker-Boden
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Publication number: 20200410037Abstract: An apparatus performs vector matrix multiplication (VMM) for an analog neural network (ANN). The apparatus includes a column of NAND flash cells in series, where each NAND flash cell includes a control gate; a bit line connected to the column of NAND flash cells, where a current drawn from the NAND flash cells flows to the bit line; an integrator connected to the bit line; and a controller having programmed instructions to control the column of NAND flash cells by setting the voltage of the control gate of each NAND flash cell.Type: ApplicationFiled: June 25, 2019Publication date: December 31, 2020Applicant: SanDisk Technologies LLCInventors: Federico Nardi, Gerrit Jan Hemink, Won Ho Choi
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Publication number: 20200400261Abstract: A pipe support device for a transformer is proposed. A brace having a grid shape and serving as a reinforcing member is provided on the surface of an outer housing constituting the exterior of the transformer. Supports are installed at predetermined intervals on the brace to be orthogonal thereto. A support base is positioned on each of the supports, and a pipe holder is coupled to the support base to support a pipe. An elastic supporting pad is positioned between the support base and the pipe and opposite flange portions of the pipe holder are seated on and coupled to the elastic supporting pad. An elastic close-contact pad is positioned between the pipe and an arched portion of the pipe holder and is brought into close contact with the pipe.Type: ApplicationFiled: December 21, 2018Publication date: December 24, 2020Inventors: Chul Jun PARK, Kyo Ho LEE, Do Jin KIM, Won Ho CHOI
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Publication number: 20200327928Abstract: A system and method for refreshing memory cells of a memory device includes storing each bit of a B-bit word in a different sub-array of a memory device. Each of the bits is associated with a bit position, and the memory device includes a plurality of sub-arrays. The system and method also include determining a refresh interval for a plurality of the bit positions based upon a relative importance of the plurality of the bit positions to a performance of a machine learning or signal processing task involving the B-bit word. The refresh interval is based upon a fidelity metric and a resource metric. The system and method further include refreshing the plurality of sub-arrays based upon the refresh interval determined for the plurality of bit positions, and dynamically updating the refresh interval for the plurality of bit positions upon receiving a new fidelity metric or a new resource metric.Type: ApplicationFiled: September 27, 2019Publication date: October 15, 2020Applicant: Western Digital Technologies, Inc.Inventors: Yongjune Kim, Won Ho Choi, Cyril Guyot, Yuval Cassuto
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Publication number: 20200311523Abstract: Use of a NAND array architecture to realize a binary neural network (BNN) allows for matrix multiplication and accumulation to be performed within the memory array. A unit synapse for storing a weight of a BNN is stored in a pair of series connected memory cells. A binary input is applied as a pattern of voltage values on a pair of word lines connected to the unit synapse to perform the multiplication of the input with the weight by determining whether or not the unit synapse conducts. The results of such multiplications are determined by a sense amplifier, with the results accumulated by a counter. The arrangement can be extended to ternary inputs to realize a ternary-binary network (TBN) by adding a circuit to detect 0 input values and adjust the accumulated count accordingly.Type: ApplicationFiled: March 28, 2019Publication date: October 1, 2020Applicant: SanDisk Technologies LLCInventors: Tung Thanh Hoang, Won Ho Choi, Martin Lueker-Boden
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Publication number: 20200311512Abstract: Use of a NAND array architecture to realize a binary neural network (BNN) allows for matrix multiplication and accumulation to be performed within the memory array. A unit synapse for storing a weight of a BNN is stored in a pair of series connected memory cells. A binary input is applied as a pattern of voltage values on a pair of word lines connected to the unit synapse to perform the multiplication of the input with the weight by determining whether or not the unit synapse conducts. The results of such multiplications are determined by a sense amplifier, with the results accumulated by a counter.Type: ApplicationFiled: June 15, 2020Publication date: October 1, 2020Applicant: SanDisk Technologies LLCInventors: Won Ho Choi, Pi-Feng Chiu, Wen Ma, Minghai Qin, Gerrit Jan Hemink, Martin Lueker-Boden
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Patent number: 10790016Abstract: Neuron circuit structures are presented which employ magnetic tunnel junction (MTJ) elements that change state probabilistically in response to application of electrical source currents that emulate synaptic activity. Some implementations form probabilistic neuron circuits using homogeneous perpendicular spin-transfer torque (STT) MTJ elements. These neuron circuits include a perpendicular STT reference MTJ element coupled via an electrical node with a perpendicular STT neuron MTJ element that can change state. The electrical node for each neuron circuit couples a neuron MTJ element or “perturbation” element to a reference element, and also to an electrical current employed to influence probabilistic magnetization state changes in the perturbation MTJ element. A read current can be applied to the perturbation element to produce an output voltage at the electrical node indicative of a magnetization state of the perturbation element.Type: GrantFiled: March 2, 2018Date of Patent: September 29, 2020Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Won Ho Choi, Young-Suk Choi
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Publication number: 20200258702Abstract: A gas circuit breaker of a gas-insulated switchgear is proposed. The gas circuit breaker includes a driving part (10) that operates when fault current occurs, and a fixed part (20) that is coupled to and separated from the driving part (10), thereby establishing electric connection. The driving part (10) includes a first main electrode (12) and a first arc electrode (14). The fixed part (20) includes a second main electrode (22) that is coupled to and separated from the first main electrode (12). The fixed part (20) also includes a second arc electrode (24). The first arc electrode (14) and the second arc electrode (24) are separated after separation of the first and second main electrodes (12, 22), thereby generating an arc. A first activation lever (30) is connected to a first connection link (19). A second activation lever (40) is connected to the first activation lever (30).Type: ApplicationFiled: May 28, 2018Publication date: August 13, 2020Inventors: Seung Kyu LEE, Kwang Jin KIM, So Hae CHOI, Chang Hwan YANG, Won Ho CHOI