Abstract: Disclosed is a BOG reliquefaction system. The BOG reliquefaction system includes: a compressor compressing BOG; a heat exchanger cooling the BOG compressed by the compressor through heat exchange using BOG discharged from a storage tank as a refrigerant; a bypass line through which the BOG is supplied to the compressor after bypassing the heat exchanger; a second valve disposed on a second supply line through which the BOG used as the refrigerant in the heat exchanger is supplied to the compressor, the second valve regulating a flow rate of fluid and opening/closing of the second supply line; and a pressure reducer disposed downstream of the heat exchanger and reducing a pressure of fluid cooled by the heat exchanger, wherein the compressor includes at least one oil-lubrication type cylinder and the bypass line is joined to the second supply line downstream of the second valve.

Abstract: The present technology relates to an electronic device. A memory system for increasing reliability of data includes a memory device including a plurality of pages, and a memory controller configured to correct an error in read data obtained by reading a selected page among the plurality of pages, and determine whether to perform a refresh operation on the selected page based on a number of error bits included in the read data. The memory controller comprises a normal read operation controller configured to control a read operation on the selected page and determine the number of error bits in the read data, an error correction performance component configured to correct the read data, and a data recovery controller configured to control the refresh operation on the selected page based on the number of error bits in the read data when the error in the read data is corrected.

Abstract: A battery diagnosis apparatus determines whether a battery may be reused and includes a data obtaining device configured to output a perturbation signal, a signal regulating device configured to generate a current by applying the perturbation signal to a battery and performing feedback of a current signal output from the battery, and a noise canceling device configured to cancel noises of the current signal and a voltage signal received from the battery. The data obtaining device outputs the perturbation signal while changing a frequency, obtains an impedance spectrum based on the noise-canceled current signal and voltage signal for each frequency, and determines whether to reuse the battery based on the obtained impedance spectrum.

Abstract: A memory device includes a plurality of memory cell arrays each configured to include a plurality of memory cells, a plurality of peripheral circuits each configured to perform operations on the plurality of memory cell arrays, a plurality of control logics configured to control the plurality of peripheral circuits, and a control logic selector configured to activate at least one control logic among the plurality of control logics according to a type of a command received from the memory controller.

Abstract: A memory system includes a first memory die including multiple planes each including a plurality of memory cells and a controller configured to perform data communication with the first memory die through a first channel, and transfer at least two commands from among commands for an erase operation, a read operation, a program operation, and a check operation to the first memory die. After transferring an erase command to a plane among the multiple planes, the controller transfers a read command, a program command, or a check command to another plane among the multiple planes while the first memory die performs an erase operation corresponding to the erase command in the plane.

Abstract: The present technology relates to a memory device. A memory device according to the present technology may include a plurality of planes, individual operation controllers configured to respectively control read operations on the plurality of planes, a common operation controller configured to control a program operation or an erase operation on any one of the plurality of planes, a command decoder configured to provide a read command among the plurality of commands to an individual operation controller that controls a plane that is indicated by an address that corresponds to the read command among the individual operation controllers, and configured to provide a program command or an erase command among the plurality of commands to the common operation controller, and a peripheral circuit configured to generate operation voltages that are used for the read operations, the program operation, and the erase operation.

Abstract: According to the present technology, a memory device may include memory cells configured to be programmed so that each of the memory cells has a threshold voltage corresponding to any one of a plurality of program states, a peripheral circuit configured to perform a read operation or a program operation on the memory cells, and control logic configured to control the peripheral circuit to perform a test read operation of reading the memory cells using a test read voltage that is any one read voltage among preset default read voltages, and perform a refresh program operation of applying a refresh program voltage to some memory cells among the memory cells according to the number of memory cells having a threshold voltage greater than the test read voltage.

Abstract: The present technology relates to an electronic device. A memory system for increasing reliability of data includes a memory device including a plurality of pages, and a memory controller configured to correct an error in read data obtained by reading a selected page among the plurality of pages, and determine whether to perform a refresh operation on the selected page based on a number of error bits included in the read data. The memory controller comprises a normal read operation controller configured to control a read operation on the selected page and determine the number of error bits in the read data, an error correction performance component configured to correct the read data, and a data recovery controller configured to control the refresh operation on the selected page based on the number of error bits in the read data when the error in the read data is corrected.

Abstract: The present technology includes a voltage generator and a memory device including the voltage generator. The voltage generator includes an operation code determiner configured to output a clock control code including the number of planes in response to an operation code, a clock group configured to simultaneously generate clocks having different periods according to the clock control code, and a pump group configured to perform a pumping operation according to the clocks and output operation voltages.

Abstract: The present disclosure relate to a semiconductor light emitting device and a method for manufacturing the same. The semiconductor light emitting device comprises a semiconductor light emitting chip, and first electrodes electrically connected to the semiconductor light emitting chip, with the first electrodes each having a planar area larger than that of the semiconductor light emitting chip, wherein lower surfaces of the first electrodes are exposed externally, and an insulating material is filled in-between inner lateral surfaces of the first electrodes.

Abstract: The present technology includes a voltage generator and a memory device including the voltage generator. The voltage generator includes an operation code determiner configured to output a clock control code including the number of planes in response to an operation code, a clock group configured to simultaneously generate clocks having different periods according to the clock control code, and a pump group configured to perform a pumping operation according to the clocks and output operation voltages.

Abstract: The present technology relates to a memory device and a method of operating the memory device. The memory device includes a target block manager configured to store a target block address on which a refresh operation is to be performed and output a refresh signal for the target block corresponding to the target block address when an auto refresh command is received, and a data transmission controller configured to output a transmission signal and a buffer control signal for transmitting data between the target block or the buffer block and the temporary buffer circuit in response to the refresh signal.

Abstract: Disclosed is a method of discharging lubricant oil from a BOG reliquefaction system configured to reliquefy BOG by compressing the BOG by a compressor, cooling the compressed BOG through heat exchange with non-compressed BOG by a heat exchanger, and reducing a pressure of fluid cooled through heat exchange by a pressure reducer. In the lubricant oil discharge method, the compressor comprises at least one oil-lubrication type cylinder and it is determined that it is time to discharge condensed or solidified lubricant oil, if at least one of preset conditions is satisfied.

Abstract: Disclosed is a BOG reliquefaction system. The BOG reliquefaction system includes: a compressor compressing BOG; a heat exchanger cooling the BOG compressed by the compressor through heat exchange using BOG discharged from a storage tank as a refrigerant; a bypass line through which the BOG is supplied to the compressor after bypassing the heat exchanger; a second valve disposed on a second supply line through which the BOG used as the refrigerant in the heat exchanger is supplied to the compressor, the second valve regulating a flow rate of fluid and opening/closing of the second supply line; and a pressure reducer disposed downstream of the heat exchanger and reducing a pressure of fluid cooled by the heat exchanger, wherein the compressor includes at least one oil-lubrication type cylinder and the bypass line is joined to the second supply line downstream of the second valve.

Abstract: A memory device includes a memory cell array, a read operator, a shift level determiner, and a read operation controller. The read operator applies a read voltage to a selected word line coupled to selected memory cells and reads the selected memory cells in response to an evaluation signal. The shift level determiner calculates a shift value indicating a difference between a number of memory cells read as on-cells and a reference number, and determines a shift level of a threshold voltage distribution for the selected memory cells. The soft read table storage stores soft read set parameters. The read operation controller determines a plurality of soft read voltages based on the shift level and the soft read set parameters and controls the read operator in response to the evaluation signal.

Abstract: A memory device includes a plurality of memory cell arrays each configured to include a plurality of memory cells, a plurality of peripheral circuits each configured to perform operations on the plurality of memory cell arrays, a plurality of control logics configured to control the plurality of peripheral circuits, and a control logic selector configured to activate at least one control logic among the plurality of control logics according to a type of a command received from the memory controller.

Abstract: A memory device includes a memory cell array, a read operator, a shift level determiner, and a read operation controller. The read operator applies a read voltage to a selected word line coupled to selected memory cells and reads the selected memory cells in response to an evaluation signal. The shift level determiner calculates a shift value indicating a difference between a number of memory cells read as on-cells and a reference number, and determines a shift level of a threshold voltage distribution for the selected memory cells. The soft read table storage stores soft read set parameters. The read operation controller determines a plurality of soft read voltages based on the shift level and the soft read set parameters and controls the read operator in response to the evaluation signal.

Abstract: The present technology relates to an electronic device. A memory device performing efficient soft decoding by reducing the number of data provided to a memory controller includes a memory cell array and a page buffer connected to the memory cell array through a bit line. The page buffer includes a plurality of latches and a read data operating component configured to generate a soft bit by logically operating soft data, which are data read from the memory cell array, and to provide the soft bit to a memory controller, in a second read operation performed when a first read operation has failed.

Abstract: Disclosed herein is a method of manufacturing an interior material, which can implement various and distinct light emission effects by disposing a light-blocking layer configured to block light emitted from a light source on a wood layer or transparent film and then allowing the component of the transparent film to fill lighting grooves formed by laser-etching. Since a tape configured to support an island is employed, stable manufacturing is possible throughout an overall process.

Abstract: A ship comprising an engine is disclosed. The ship comprising an engine comprises: a self-heat exchanger which heat-exchanges boil-off gas discharged from a storage tank; a multi-stage compressor which compresses, in multi-stages, boil-off gas that passed through the self-heat exchanger after being discharged from the storage tank; a first decompressing device which expands one portion of boil-off gas that passed through the self-heat exchanger after being compressed by the multi-stage compressor; and a second decompressing device which expands the other portion of the boil-off gas that passed through the self-heat exchanger after being compressed by the multi-stage compressor, wherein the self-heat exchanger uses boil-off gas discharged from the storage tank and boil-off gas expanded by the first decompressing device as refrigerants for cooling boil-off gas compressed by the multi-stage compressor.