Abstract: The present invention relates to a parallel multithread processor (1) with split contexts, with M parallel-connected standard processor root units (2) being provided for instruction execution of program instructions for different threads (T), and with N context memories (3) being provided, which each temporarily store a current state of a thread (T), and with a thread monitoring unit (4) being provided, by means of which each standard processor root unit (2) can be connected to each context memory (3). The invention accordingly provides a processor architecture in which a number N of different context memories (3) and corresponding threads (T) are effectively fully networked with a number M of standard processor root units (2). This means that use is made not only of paralleling of the standard processor root units (2), but also of the threads (T) and of the context memories (3).

Abstract: A computing device includes a hardware data processing unit having at least one input buffer, a plurality of output buffers, a data transfer unit, and a software control unit, the data transfer unit configured to transfer data from the input buffer to the plurality of output buffers, and the software control unit configured to control the data transfer unit.

Abstract: In a method for forwarding data packets in a network a circuit comprises a data storage and a control device. Each data packet has a destination address and the data storage comprises T data sub-storages for storing all network addresses which are coded by a particular coding method on the basis of their respective key bit length in precisely one of the data sub-storages. The t-th data sub-storage is divided into blocks having D data elements of identical data element bit length, where t?[1, . . . , T] and D is the smallest common multiple of t?[1, . . . , T].

Abstract: A method and a programmable unit for bit field shifting in a memory device in a programmable unit as a result of the execution of an instruction, in which a bit segment is shifted within a first memory unit to a second memory unit, are presented. The bit segment is read with a first bit length from a first bit field in the first memory unit starting at a first start point. The bit segment that has been read is stored in the first bit field in the second memory unit starting at a second start point. The first or the second start points is updated by a predetermined value and the updated start point is stored for subsequent method steps.

Abstract: A unit for distributing and processing data packets has an administration unit for distributing the data packets to parallel-connected processor units. In this case, the processors of adjacent processor units have intermediate connections for interchanging data. The administration unit distributes the data packets in dependence on administration information for the data packets and/or on operating information for the processor units.

Abstract: A device (1) to control processing of data elements (data_i), in which a thread is assigned to each data element (data_i), comprises a first unit (CS), which, during a first cycle, fetches an instruction (cs_ir_s) that is entered in the context of the thread assigned to the incoming data element (data_i), a second unit (IF), which, during a second cycle, fetches an instruction (if_ir_s) that succeeds a stipulated instruction in a stipulated thread, and a third unit (ID), which, during the second cycle, decodes the instruction prescribed for processing of the data element (data_i) and generates a data element processing signal (dec_o).

Abstract: To enable data packets, which can be present in different data transmission formats and which are to be routed in a communication network, to be stored as simply and effectively as possible, it is proposed in accordance with the invention to generate for each data packet to be stored a descriptor (8) having a special data structure, the descriptor (8) comprising, in particular, a data field (14) with a pointer array. The data of the data packet to be stored are stored in a memory (1) which comprises a multiplicity of memory blocks (7) of the same size. The pointer array of the descriptor (8) points to the start addresses of the memory blocks (7) needed for storing the data packet.

Abstract: The invention relates to a heterogeneous parallel multithread processor (1) with shared contexts which has a plurality (M) of parallel-connected standard processor root unit types (2p; p? [1, . . . , M]), where each respective standard processor root unit type (2p) has at least one or more (K) parallel-connected standard processor root units (2pq; q? [1, . . . , K]) for instruction execution of program instructions from various threads (T), each standard processor root unit type (2p) having N local context memories (32pt) which each buffer-store part of a current processor state for a thread. The multithread processor (1) also has a plurality (N) of global context memories (3t; t? [1, . . . , N]) which each buffer-store part of a current processor state for a thread, and a thread control unit (4) which can connect any standard processor root unit (2pq) to any global context memory (3t).

Abstract: A processor comprises checking and control devices, first register, and register bank. The control device checks a condition or a subcondition of the condition within a first time unit based on a first subcondition checked within a second time unit preceding the first time unit, a second subcondition checked within a third time unit preceding the second time unit, and a single condition. The first register is coupled to the control device for storing the checked condition and the output of the first register is coupled to the control device for providing the stored, checked subcondition as a checked, first subcondition. The input of the register bank is coupled to the first register for receiving the stored, checked subcondition, the second register stores the received, checked subcondition as the checked, second subcondition, and the register bank is coupled to the control device for providing the checked, second subcondition.

Abstract: The invention relates to a processor system which is configured as a communications controller and which comprises a central processor unit (1) for executing instructions filed in a program memory (8), whereby the processor unit (1) comprises only one path (2,3) for reading out an instruction from the program memory (8) and for decoding the instruction. In addition, several parallelly operable execution paths (4,5;6,7) for parallelly executing different program flows are provided which each access the path (2,3) jointly used for reading out and decoding an instruction.

Abstract: A server module for a modularly designed server (1) having at least one data processing unit (17) for data processing data packets, at least one addressable communication interface (19) for connecting the server module (2, 3, 4, 5) to an external network (13) via which the data packets are transmitted, a switching interface (20) for connecting the server module (2, 3, 4, 5) to a switching device (7) of the modularly designed server (1); and having a routing calculation unit (18) for calculating a server module address using a routing table on the basis of the utilization level of the data processing units of all the server modules (2, 3, 4, 5) of the modularly designed server (1).

Abstract: A method for timing the output of data packets from network nodes, in which the current fill level of the buffer memory of a queue of the network node is first determined. The determined fill level of the buffer memory is compared with a predetermined lower limit for the fill level of the buffer memory. The output time of a data packet is assigned in dependence on the result of the comparison.

Abstract: High speed processor having a data processing unit (13) for processing data, a data memory (20) which is connected to the data processing unit via a data bus (10) and can be addressed by the data processing unit (13) via a data memory address bus (18), at least one input interface buffer (9) which is connected to the data bus (10) and has the purpose of buffering input data, at least one output interface buffer (16) which is connected to the data bus (10) and has the purpose of buffering output data, the input interface buffer (9) and the output interface buffer (26) being directly addressable by the data processing unit (13) via an interface address bus (24).

Abstract: High-speed router for transmitting data packets, containing header data and useful data, between data networks, the router including a plurality of data processing processors for parallel data processing of the header data, a demultiplexer for separating the data packets into header data and useful data, and a distribution processor for distributing the separated header data among the data processing processors. The distribution processor distributes the header data at least in part on the basis of a priority specified by the header data and the workload of the data processing processors.

Abstract: In order to be able to use a smaller routing table (4) and, thus, to reduce the costs and power consumption and to improve the performance of an IP router, it is proposed to extract a destination address identifier (ADR) from a data packet to be forwarded by the IP router, compress the extracted destination address identifier (ADR) by using a lossless data compression algorithm, and compare the compressed destination address identifier with entries stored in the routing table (4) so as to find a correspondence between the destination address identifier and one of the entries of the routing table (4). Each entry of the routing table (4) corresponds to a possible or available forwarding address of the IP router, the forwarding addresses having been compressed with the same data compression algorithm as the destination address identifier.

Abstract: In a method for forwarding data packets in a network a circuit comprises a data storage and a control device. Each data packet has a destination address and the data storage comprises T data sub-storages for storing all network addresses which are coded by a particular coding method on the basis of their respective key bit length in precisely one of the data sub-storages. The t-th data sub-storage is divided into blocks having D data elements of identical data element bit length, where t?[1, . . . , T] and D is the smallest common multiple of t?[1, . . . , T].

Abstract: A method and a programmable unit for bit field shifting in a memory device in a programmable unit as a result of the execution of an instruction, in which a bit segment is shifted within a first memory unit to a second memory unit, are presented. The bit segment is read with a first bit length from a first bit field in the first memory unit starting at a first start point. The bit segment that has been read is stored in the first bit field in the second memory unit starting at a second start point. The first or the second start points is updated by a predetermined value and the updated start point is stored for subsequent method steps.

Abstract: The invention relates to a method for changing the image size of video images, in which a decimation of video image signals (V) by an integral decimation factor (MHD, MVD) is carried out, and the decimated video image signals are subsequently read into an image memory for buffering. In order to achieve better possibilities of adjusting the image reduction with a relatively low outlay and high image quality, a fine decimation of the video image signals (V) is additionally carried out before buffering by a fine decimation factor (SHS, SVS) which can be adjusted to non-integral values, and a total decimation factor (MH, MV) relevant to the decimation of the video image signals (V) is formed from the integral decimation factor (MHD, MVD) and the fine decimation factor (SHS, SVS).

Abstract: The present invention relates to a parallel multithread processor (1) with split contexts, with M parallel-connected standard processor root units (2) being provided for instruction execution of program instructions for different threads (T), and with N context memories (3) being provided, which each temporarily store a current state of a thread (T), and with a thread monitoring unit (4) being provided, by means of which each standard processor root unit (2) can be connected to each context memory (3). The invention accordingly provides a processor architecture in which a number N of different context memories (3) and corresponding threads (T) are effectively fully networked with a number M of standard processor root units (2). This means that use is made not only of paralleling of the standard processor root units (2), but also of the threads (T) and of the context memories (3).

Abstract: The invention relates to a heterogeneous parallel multithread processor (1) with shared contexts which has a plurality (M) of parallel-connected standard processor root unit types (2p; p?[1, . . . , M]), where each respective standard processor root unit type (2p) has at least one or more (K) parallel-connected standard processor root units (2pq; q?[1, . . . , K]) for instruction execution of program instructions from various threads (T), each standard processor root unit type (2p) having N local context memories (32pt) which each buffer-store part of a current processor state for a thread. The multithread processor (1) also has a plurality (N) of global context memories (3t; t?[1, . . . , N]) which each buffer-store part of a current processor state for a thread, and a thread control unit (4) which can connect any standard processor root unit (2pq) to any global context memory (3t).