Abstract: The circuit simultaneously filters and decimates a video signal formed with samples for luminance and chrominance. A subcircuit provides the samples in distinct sequences with alternate luminance and chrominance values. A filter stage is provided which contains a first adder which is supplied with one of the sequences via a first register. The other terminal of the adder is supplied with the other sequence. A second register can be directly connected to the adder if luminance samples are processed, and via a third register if chrominance samples are processed. The output signal of the second register is combined with the samples of one of the sequences by means of an adder at the output end. In the case of a higher degree of the filter, a number of filter stages are cascaded (connected in series). Where a higher degree of decimation is required, feedback is provided in each filter stage.