Abstract: A multithread processor based on the inventive architecture is a clocked multithread processor (1) for data processing of N threads by means of a standard processor root unit (2), wherein a thread Tj which is to be processed at any given time by the standard processor root unit (2) can be switched without any clock cycle loss by means of a switching trigger signal (UTS) to another thread T1, wherein the switching trigger signal (UTS) is generated as a consequence of a program instruction (which is fetched from a program instruction memory (3) and implies a latency time) for the thread Tj which is to be processed at that time and results in a latency time for the standard processor root unit (2), before the program instruction which has been fetched and implies a latency time is decoded by the standard processor root unit (2).

Abstract: A multithread processor according to the inventive architecture is a clocked multithread processor for data processing of threads having a standard processor root unit (1) in which threads can be switched to a different thread T1 by means a thread switching trigger data field (11), triggered by the thread Tj which is currently to be processed by the standard processor root unit (1), without any clock cycle loss, with each program instruction Ijk for a thread Tj having a thread switching trigger data field (11) such as this.

Abstract: A method for compressing a data packet is proposed, the data packet comprising at least a first data block and a second data block, the first data block referring to the second data block. In the method, the second data block is compressed and it is noted in the data packet that the second data block has been compressed. In one embodiment, the method is suitable for IPv6 data packets, the second data block then being, for example, a routing header.

Abstract: In a processor system, different memory means (8), which can in each case comprise a memory stack (9) for the instruction counter, a register (10) for temporarily storing data and status register (11), are provided for various tasks. When an interrupt event (EV) occurs which causes a change from a current task to a new task, a controller (21) switches from the memory means (8) allocated to the old task to the memory means (8) allocated to the new task.

Abstract: A network comprises routers, wherein at least some of the routers are configured to receive a number of datastreams and to output an aggregated datastream. Subject to the precondition that a limiting bit rate ri and a number of burst bits bi can be quoted for each datastream i supplied to a router from outside the network, such that the number Aiin(t1, t2) of data bits which are received at an input of the routers, between a time t1 and a later time t2, satisfies the relationship Aiin(t1, t2)?ri*(t2?t1)+bi, each router j controls the output of data packets in the aggregated datastream ia(j) such that, for a limiting bit rate Ria(j)ag and for a predeterminable burst bit number Bia(j), the number Aia(j)out(t1, t2) of data bits output in the aggregated datastream ia(j) satisfies the relationship Aia(j)out(t1, t2)?Ria(j)ag*(t2?t1)+Bia(j), wherein Ria(j)ag and Bia(j) are independent of the observation time period.

Abstract: Multichannel processor for processing data of multi-protocol data packets, comprising (a) a number of input ports (2) for receiving received data packets in parallel, which can be selected in each case by means of an input port number; (b) at least one multiplexer (3) connected to the input ports (2), which switches through the data present at the selected input port word by word; (c) at least one first programmable data processing unit (4), which separates the sequence of data words switched through by the multiplexer (3) into data packet header words and into data packet payload words in accordance with a sorting program selected in accordance with the input port number; (d) a buffer management unit (44) which writes the data packet payload words of a received data packet into an addressable payload memory (47) and generates localization data which specify the corresponding memory area; (e) a descriptor generator unit (43) for generating data packet descriptors which in each case contain a header assembled

Abstract: A device (1) to control processing of data elements (data_i), in which a thread is assigned to each data element (data_i), comprises a first unit (CS), which, during a first cycle, fetches an instruction (cs_ir_s) that is entered in the context of the thread assigned to the incoming data element (data_i), a second unit (IF), which, during a second cycle, fetches an instruction (if_ir_s) that succeeds a stipulated instruction in a stipulated thread, and a third unit (ID), which, during the second cycle, decodes the instruction prescribed for processing of the data element (data_i) and generates a data element processing signal (dec_o).

Abstract: The circuit takes into account whether the image on a screen is too bright, whether more than one specific number of pixels have a luminance value that is greater than a given peak value and whether this condition is met in more than one specific number of lines in a picture and in more than one specific number of successive images with one such number of lines.

Abstract: In orthogonal frequency division modulation, use is made of the fact that the individual carriers which are transmitted on the principle of frequency multiplexing are orthogonal to one another. The modulation can then be carried out relatively simply using discrete Fourier transformation. Sicne the calculation of the discrete Fourier transformation involves a large number of multiplications, the bit data which are intended to be modulated onto the carriers are combined in each case to form a two-dimensional vector. The vector is supplied to a two-dimensional inverse Fourier transformation as the input variable. The number of multiplications required is thus reduced. The invention is particularly suitable for transmission of broadcast radio, television and mobile radio signals.

Abstract: A unit for distributing and processing data packets has an administration unit for distributing the data packets to parallel-connected processor units. In this case, the processors of adjacent processor units have intermediate connections for interchanging data. The administration unit distributes the data packets in dependence on administration information for the data packets and/or on operating information for the processor units.

Abstract: A filter for filtering n data trains by time division multiplexing includes data channels for receiving data train values, registers subdivided into n groups for buffer storage of the data train values or derived values, and adders each having inputs. Each of the n groups is connected to one of the data channels. The adders and the registers alternatively connect to form a chain. The first input of respective adders connected upstream of a respective register of an ith group (0≦i≦n−1) has a connection to respective data channels assigned to the ith group, and the second input is connected to a respective register of a group having a number (i−1)mod n without an intervening register of another group. The filter is used to parallelly decimate data trains by a common factor. A filter configuration includes the filter and two multipliers. A method is also provided.

Abstract: To enable data packets, which can be present in different data transmission formats and which are to be routed in a communication network, to be stored as simply and effectively as possible, it is proposed in accordance with the invention to generate for each data packet to be stored a descriptor (8) having a special data structure, the descriptor (8) comprising, in particular, a data field (14) with a pointer array. The data of the data packet to be stored are stored in a memory (1) which comprises a multiplicity of memory blocks (7) of the same size. The pointer array of the descriptor (8) points to the start addresses of the memory blocks (7) needed for storing the data packet.

Abstract: A method for timing the output of data packets from network nodes, in which the current fill level of the buffer memory of a queue of the network node is first determined. The determined fill level of the buffer memory is compared with a predetermined lower limit for the fill level of the buffer memory. The output time of a data packet is assigned in dependence on the result of the comparison.

Abstract: The method suppresses noise in a one-dimensional or multi-dimensional signal. A plurality of estimates for the noise-free useful signal are carried out on the basis of a measurement of the noisy signal, and each estimated value for each point is individually assigned a preference. A new estimated value for the useful signal is formed from the individual estimated values by arithmetic averaging weighted by the preference.

Abstract: High speed processor having a data processing unit (13) for processing data, a data memory (20) which is connected to the data processing unit via a data bus (10) and can be addressed by the data processing unit (13) via a data memory address bus (18), at least one input interface buffer (9) which is connected to the data bus (10) and has the purpose of buffering input data, at least one output interface buffer (16) which is connected to the data bus (10) and has the purpose of buffering output data, the input interface buffer (9) and the output interface buffer (26) being directly addressable by the data processing unit (13) via an interface address bus (24).

Abstract: A network comprises routers, wherein at least some of the routers are configured to receive a number of datastreams and to output an aggregated datastream. Subject to the precondition that a limiting bit rate ri and a number of burst bits bi can be quoted for each datastream i supplied to a router from outside the network, such that the number Aiin(t1, t2) of data bits which are received at an input of the routers, between a time t1 and a later time t2, satisfies the relationship Aiin(t1, t2)≦ri*(t2−t1)+bi, each router j controls the output of data packets in the aggregated datastream ia(j) such that, for a limiting bit rate Ria(j)ag and for a predeterminable burst bit number Bia(j), the number Aia(j)out(t1, t2) of data bits output in the aggregated datastream ia(j) satisfies the relationship Aia(j)out(t1, t2)≦Ria(j)ag*(t2−t1)+Bia(j), wherein Ria(j)ag and Bia(j) are independent of the observation time period.

Abstract: A digital de-emphasis filter for a SECAM decoder for converting a sequence of input image data into filtered image data includes at least one recursion register for storing an auxiliary value that is obtained using an input image data value. An arithmetic circuit uses the auxiliary value and a newly input image data value to generate a new auxiliary value, which replaces the contents of the recursion register, and a filtered image data value. To determine the achromatic value in addition to performing de-emphasis filtering, the filter is provided with a device for storing and outputting a value representative of an estimated value of the achromatic value of the SECAM signal, and a first switch for applying and registering the output estimated value into the recursion register at the beginning of each burst gate period of the SECAM signal.

Abstract: A server module for a modularly designed server (1) having at least one data processing unit (17) for data processing data packets, at least one addressable communication interface (19) for connecting the server module (2, 3, 4, 5) to an external network (13) via which the data packets are transmitted, a switching interface (20) for connecting the server module (2, 3, 4, 5) to a switching device (7) of the modularly designed server (1); and having a routing calculation unit (18) for calculating a server module address using a routing table on the basis of the utilization level of the data processing units of all the server modules (2, 3, 4, 5) of the modularly designed server (1).

Abstract: High-speed router for transmitting data packets, containing header data and useful data, between data networks, the router (1) having a plurality of data processing processors (12, 13, 14, 15) for parallel data processing of the header data.

Abstract: A data-processing device, in particular a network processor for processing layer 1 to 7 of protocol stacks in applications such as LAN, ATM switches, IP routers or frame relays which are based on DSL, Ethernet or cable modems. The processor has instruction buffers, instruction decoders, and instruction-execution units corresponding to a number of processes to be processed in parallel. A program flow control unit essentially controls the parallel processing.