Abstract: Provided are a tripeptide compound, a preparation method therefor, and an application thereof. The structure of the related compound is represented by formula (I). The provided compound has angiotensin converting enzyme inhibiting bioactivity, and the compound and a pharmaceutical composition thereof play a role in preventing and treating hypertension and other cardiocerebral vascular system diseases.

Abstract: The present invention proposes a GOA circuit and a display device adopting the same. The GOA circuit includes thirteen transistors and a first capacitor. The GOA circuit can be driven in 2D and 3D driving modes to prolong charging time of each pixel. Each two GOA circuit units share a set of Nth stage start pulse signals, Nth stage gate pulse signals and eight clock pulse signals. Because the charging time of each pixel is prolonged, the display device can show images with better display quality.

Abstract: The present invention provides a manufacture method of a TFT array substrate and a TFT array substrate structure, and the TFT array substrate structure comprises a substrate (1), a first metal electrode (2) on the substrate (1), a gate isolation layer (3) positioned on the substrate (1) and completely covering the first metal electrode (2), an island shaped semiconductor layer (4) on the gate isolation layer (3), a second metal electrode (6) on the gate isolation layer (3) and the island shaped semiconductor layer (4), a protecting layer (8) on the second metal electrode (6), a color resist layer (7) on the protecting layer (8), a protecting layer (12) on the color resist layer (7) and a first pixel electrode layer (9) on the protecting layer (12); a via (81) is formed on the protecting layer (8), the color resist layer (7) and the protecting layer (12), and an organic material layer (10) fills the inside of the via (81).

Abstract: An array substrate and a manufacturing method thereof are provided. The method has steps of: forming a buffer layer, a light-shading layer, and a whole semiconductor layer on a substrate; simultaneously patterning the semiconductor layer and the light-shading layer; and forming a first insulation layer, a first metal layer, a second insulation layer, a second metal layer, a flat layer, and a first transparent conductive layer on the patterned semiconductor layer.

Abstract: The invention relates to a method for preparing a homodimer protein mixture by using repulsive interaction of charges. The method comprises the step of replacing part of residues with the opposite-charged residues, so that different proteins or antibodies are unfavorable to forming heterodimers due to the repulsive interaction between like charges, while same proteins or antibodies are favorable to forming homodimers due to attractive interaction between opposite charges. The homodimer protein mixture obtained according to the method of the invention can simultaneously act on different epitopes of the same target, and simultaneously inhibit the effects of a plurality of antigens by binding to the antigens from different sources, thereby providing a new approach towards immunological diagnosis and treatment of tumors and other diseases.

Abstract: A GOA (Gate driver On Array) for an LCD (Liquid Crystal Display) device is disclosed herein. The LCD device comprises a plurality of scanning lines. The GOA circuit comprises a plurality of GOA units, which are cascaded with each other as a plurality of level GOA units. The (n)th level GOA unit comprises a clock circuit, a pull-down circuit, a bootstrap capacitor circuit, a pull-up circuit, and a pull-down sustain circuit, to improve the color shift issue of a Tri-gate.

Abstract: The present invention provides a LTPS array substrate and a manufacturing method thereof. The method comprises: forming a source electrode and a drain electrode on a substrate, forming polysilicon layers of a first region and a second region on the substrate including the source electrode and the drain electrode, and the thickness of the polysilicon layer of the first region is greater than the one of the second region, the polysilicon layer of the first region partially covers the source electrode and the drain electrode; passivating the surface of the polysilicon layer in order to turn the part of the adjacent surface of the polysilicon layer of the second region and the first region into an insulating layer; forming a gate electrode on the insulating layer between the source electrode and the drain electrode. The present invention can simplify the LTPS technical process and reduce the producing costs.

Abstract: A scan driving method for a display panel is disclosed. The display panel has a pixel driving circuit including n scanning lines and m data lines; and the scanning lines and the data lines intersect each other to define a plurality of pixel units. The scan driving method includes a step of enabling the xth scanning line by a clock signal having a duty cycle not more than 45%, and meanwhile enabling the (x+2)th scanning line, where x is an positive integer and 1?x?n?2.

Abstract: A transient IR-drop waveform measurement system and method for a high speed integrated circuit are provided. The system includes all-digital elements and is based on a ring oscillator in GHz. Through oscillation with a Fast Ring Oscillator, sampling with an Edge Detector and counting with a Ripple Counter, a width and a peak of an IR-drop waveform are obtained. Moreover, a power supply network is adapted during a clock cycle through sending an adaptation signal to a connected dynamic voltage frequency scaling (DVFS) system. The measurement method includes 11 steps. The measurement system has following features: 1) IR-drop peak/width measurement ability; 2) low fabrication and test cost; 3) high accuracy and sensitivity; 4) early adaptation ability. Therefore, the measurement system can be used alone for chip monitoring or testing, in order to reduce a power supply noise disturbance to a chip.

Abstract: The present invention provides a manufacture method of a TFT array substrate and a TFT array substrate structure, and the TFT array substrate structure comprises a substrate (1), a first metal electrode (2) on the substrate (1), a gate isolation layer (3) positioned on the substrate (1) and completely covering the first metal electrode (2), an island shaped semiconductor layer (4) on the gate isolation layer (3), a second metal electrode (6) on the gate isolation layer (3) and the island shaped semiconductor layer (4), a protecting layer (8) on the second metal electrode (6), a color resist layer (7) on the protecting layer (8), a protecting layer (12) on the color resist layer (7) and a first pixel electrode layer (9) on the protecting layer (12); a via (81) is formed on the protecting layer (8), the color resist layer (7) and the protecting layer (12), and an organic material layer (10) fills the inside of the via (81).

Abstract: The present invention proposes a low temperature poly-silicon thin-film transistor having a dual-gate structure and a method for forming the low temperature poly-silicon thin-film transistor. The low temperature poly-silicon thin-film transistor includes: a substrate, one or more patterned amorphous silicon (a-Si) layers, disposed in a barrier layer on the substrate, for forming a bottom gate, an NMOS disposed on the barrier layer, and a PMOS disposed on the barrier layer. The NMOS comprises a patterned gate electrode (GE) layer as a top gate, and the patterned GE layer and the bottom gate formed by the one or more patterned a-Si layers form a dual-gate structure. The present invention proposes a low temperature poly-silicon thin-film transistor with a more stabilized I-V characteristic, better driving ability, low power consumption, and higher production yield.

Abstract: The present invention proposes a low temperature poly-silicon thin-film transistor having a dual-gate structure and a method for forming the low temperature poly-silicon thin-film transistor. The low temperature poly-silicon thin-film transistor includes: a substrate, one or more patterned amorphous silicon (a-Si) layers, disposed in a barrier layer on the substrate, for forming a bottom gate, an NMOS disposed on the barrier layer, and a PMOS disposed on the barrier layer. The NMOS comprises a patterned gate electrode (GE) layer as a top gate, and the patterned GE layer and the bottom gate formed by the one or more patterned a-Si layers form a dual-gate structure. The present invention proposes a low temperature poly-silicon thin-film transistor with a more stabilized I-V characteristic, better driving ability, low power consumption, and higher production yield.

Abstract: The present disclosure provides substantially monodisperse random coil polypeptides, vectors encoding the polypeptides, conjugates containing the polypeptides, methods for their preparation, and their uses in nucleic acid separations, DNA sequencing, and other applications requiring high monodispersity.

Abstract: System circuitry includes a logic circuit having an input and an output that is a functional element of the system circuitry. Pattern application circuitry is coupled to the input of the logic circuit and provides an input pattern to the input of the logic circuit. The input pattern has a valid signature based upon a comparison of the input and the output of the logic circuit when the logic circuit is functioning properly. A logic comparator is coupled to the input and the output of the logic circuit and generates pulses in response to the input pattern. A counter is coupled to the logic comparator that obtains a count of the pulses generated by the logic comparator in response to the input pattern. A signature comparator is coupled to the counter and generates a warning signal if the valid signature is different from the count.

Abstract: The invention relates to a method for preparing a homodimer protein mixture by using repulsive interaction of charges. The method comprises the step of replacing part of residues with the opposite-charged residues, so that different proteins or antibodies are unfavorable to forming heterodimers due to the repulsive interaction between like charges, while same proteins or antibodies are favorable to forming homodimers due to attractive interaction between opposite charges. The homodimer protein mixture obtained according to the method of the invention can simultaneously act on different epitopes of the same target, and simultaneously inhibit the effects of a plurality of antigens by binding to the antigens from different sources, thereby providing a new approach towards immunological diagnosis and treatment of tumors and other diseases.

Abstract: The present invention provides a TFT substrate and a liquid crystal display panel using the TFT substrate. The TFT substrate includes: first and second sharing capacitors (2, 4) that are connected in parallel. The first sharing capacitor (2) includes a first upper substrate (22), a first lower substrate (24) opposite to the first upper substrate (22), and a first semiconductor layer (26) arranged between the first upper substrate (22) and the first lower substrate (24). The second sharing capacitor (4) includes a second upper substrate (42), a second lower substrate (44) opposite to the second upper substrate (42), and a second semiconductor layer (46) arranged between the second upper substrate (42) and the second lower substrate (44). The first upper substrate (22) of the first sharing capacitor (2) and the second lower substrate (44) of the second sharing capacitor (4) are electrically connected to the pixel electrode (6).

Abstract: A data processing system on an integrated circuit includes a core that performs switching operations responsive to a system clock that draws current from the power supply network. An IR-drop detector includes a resistor ladder having outputs representative of an IR-drop caused by the core during the switching operations. The system further includes a plurality of amplifiers coupled to the outputs indicative of the IR-drop, a plurality of flip-flops coupled to the amplifiers, and a variable clock generator. The variable clock generator outputs a sampling clock comprising a group consisting of a variable phase or a variable frequency to the plurality of flip-flops. The flip-flops are triggered by the sampling clock so that the IR-drop at a time during a clock cycle of the system clock can be detected, and the peak IR-drop value for can be tracked.

Abstract: System circuitry includes a logic circuit having an input and an output that is a functional element of the system circuitry. Pattern application circuitry is coupled to the input of the logic circuit and provides an input pattern to the input of the logic circuit. The input pattern has a valid signature based upon a comparison of the input and the output of the logic circuit when the logic circuit is functioning properly. A logic comparator is coupled to the input and the output of the logic circuit and generates pulses in response to the input pattern. A counter is coupled to the logic comparator that obtains a count of the pulses generated by the logic comparator in response to the input pattern. A signature comparator is coupled to the counter and generates a warning signal if the valid signature is different from the count.

Abstract: Aspects of the disclosure relate to combining on-chip structure with external current measurements for threat detection in an integrated circuit. This method considers Trojans' impact on neighboring cells and on the entire IC's power consumption, and effectively localizes the measurement of dynamic power. An on-chip structure can permit threat detections. In one aspect, the on-chip structure can comprise a plurality of sensors distributed across the entirety of the IC, with each sensor of the plurality of sensors being placed in different rows of a standard-cell design. In another aspect, data analysis can permit separating effect of process variations on transient power usage of the IC from effects of a hardware threat such power usage. The on-chip structure also can be employed for implementation of a PE-PUF.

Abstract: A data processing system on an integrated circuit includes a core that performs switching operations responsive to a system clock that draws current from the power supply network. An IR-drop detector includes a resistor ladder having outputs representative of an IR-drop caused by the core during the switching operations. The system further includes a plurality of amplifiers coupled to the outputs indicative of the IR-drop, a plurality of flip-flops coupled to the amplifiers, and a variable clock generator. The variable clock generator outputs a sampling clock comprising a group consisting of a variable phase or a variable frequency to the plurality of flip-flops. The flip-flops are triggered by the sampling clock so that the IR-drop at a time during a clock cycle of the system clock can be detected, and the peak IR-drop value for can be tracked.