Patents by Inventor Yan A. Borodovsky

Yan A. Borodovsky has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090042111
    Abstract: Systems and techniques for lithography. In one aspect, a method includes producing a microelectronic device by modulating an intensity and a phase of the zero diffraction order of a radiation with a device including subwavelength features having a pitch dimension smaller than one wavelength of the radiation.
    Type: Application
    Filed: October 20, 2008
    Publication date: February 12, 2009
    Applicant: Intel Corporation
    Inventors: EDITA TEJNIL, Yan Borodovsky
  • Patent number: 7438997
    Abstract: Systems and techniques for lithography. In one aspect, a method includes producing a microelectronic device by modulating an intensity and a phase of the zero diffraction order of a radiation with a device including subwavelength features having a pitch dimension smaller than one wavelength of the radiation.
    Type: Grant
    Filed: May 14, 2004
    Date of Patent: October 21, 2008
    Assignee: Intel Corporation
    Inventors: Edita Tejnil, Yan Borodovsky
  • Patent number: 7254803
    Abstract: Systems and techniques for generating test structures. The test structures may conform to a set of design rules for a portion of an integrated circuit design. The test structures may include base figures, which may be in an enriched environment. For example, the test structures may include one or more additional figures such as surrounding figures, external figures, and/or symmetric figures. A correction algorithm for correcting a layout may be checked using a plurality of the test structures.
    Type: Grant
    Filed: September 30, 2004
    Date of Patent: August 7, 2007
    Assignee: Intel Corporation
    Inventors: Seongtae Jeong, Yan Borodovsky
  • Patent number: 7245352
    Abstract: Systems and techniques for alignment with latent images. In one implementation, a method includes detecting a location of a latent image on a substrate, repositioning the substrate based on the detected location of the latent image, and patterning the substrate.
    Type: Grant
    Filed: July 20, 2004
    Date of Patent: July 17, 2007
    Assignee: Intel Corporation
    Inventors: Yan Borodovsky, Ilya Grodnensky
  • Publication number: 20070094959
    Abstract: The present invention discloses a method of designing a set of two tiled masks, as well as, a mask including: a first tile, the first tile being transparent to a light, the first tile having a first characteristic linear dimension that is 15% or less of a wavelength of the light; a second tile, the second tile being transparent to the light, the second tile having a second characteristic linear dimension that is 15% or less of the wavelength of the light; and a third tile, the third tile being opaque to the light, the third tile having a third characteristic linear dimension that is 15% or less of the wavelength of the light.
    Type: Application
    Filed: September 30, 2005
    Publication date: May 3, 2007
    Inventors: Bin Hu, Vivek Singh, Yan Borodovsky
  • Publication number: 20070090084
    Abstract: A reclaim method for an extreme ultraviolet mask blank and associated products are generally described. In this regard, according to one example embodiment, a reclaim method comprises removing an outer capping layer from a multilayer (ML) stack, the ML stack having been deposited on an inner capping layer, removing the ML stack, and depositing a new ML stack on the inner capping layer, the inner capping layer having an inner thickness that is selected to enable constructive interference between the new ML stack and a ML reflector beneath the inner capping layer.
    Type: Application
    Filed: October 20, 2005
    Publication date: April 26, 2007
    Inventors: Pei-Yang Yan, Yan Borodovsky
  • Publication number: 20070077500
    Abstract: The present invention discloses a mask including: a first region near a corner of a feature, the first region including a first element, the first element being transparent to a light, the first element having a side that is smaller than a wavelength of said light; a second region near the corner of the feature, the second region including a second element, the second element being transparent to the light, the second element having a side that is smaller than the wavelength of the light; and a third region near the corner of the feature, the third region including a third element, the third element being opaque to the light, the third element having a side that is smaller than the wavelength of the light.
    Type: Application
    Filed: September 30, 2005
    Publication date: April 5, 2007
    Inventors: Bikram Baidya, Vivek Singh, Yan Borodovsky
  • Publication number: 20070002322
    Abstract: Embodiments of the invention provide methods and apparatuses for detecting defects and contaminants on reticles. For one embodiment of the invention, either one or both of an aerial image database and a resist image database are created and compared to an actual scanned mask die image. For one embodiment of the invention, the comparison is used to identify defects of contaminants on the reticle. For one embodiment of the invention, a decision as to whether the reticle should be discarded or cleaned and repaired is made based upon the determined defects or contaminants.
    Type: Application
    Filed: June 30, 2005
    Publication date: January 4, 2007
    Inventors: Yan Borodovsky, Wen-Hao Cheng
  • Publication number: 20070006113
    Abstract: A pixelated photolithography mask is optimized for high resolution microelectronic processing. In one embodiment, the invention includes synthesizing a pixelated photolithography mask, applying a pixel flipping function to the mask, comparing the resulting mask to a desired result, and synthesizing an optimized pixelated binary photolithography mask using the function.
    Type: Application
    Filed: June 30, 2005
    Publication date: January 4, 2007
    Inventors: Bin Hu, Vivek Singh, Bikram Baidya, Kenny Toh, Srinivas Bollepalli, Yan Borodovsky
  • Patent number: 7142282
    Abstract: A device that includes contacts. In one implementation, a device includes a substantially arbitrary arrangement of contacts. The contacts in the device are defined with a definition characteristic of interference lithography.
    Type: Grant
    Filed: October 17, 2003
    Date of Patent: November 28, 2006
    Assignee: Intel Corporation
    Inventor: Yan Borodovsky
  • Publication number: 20060075366
    Abstract: Systems and techniques for generating test structures. The test structures may conform to a set of design rules for a portion of an integrated circuit design. The test structures may include base figures, which may be in an enriched environment. For example, the test structures may include one or more additional figures such as surrounding figures, external figures, and/or symmetric figures. A correction algorithm for correcting a layout may be checked using a plurality of the test structures.
    Type: Application
    Filed: September 30, 2004
    Publication date: April 6, 2006
    Inventors: Seongtae Jeong, Yan Borodovsky
  • Publication number: 20060017910
    Abstract: Systems and techniques for printing substrates. In one implementation, a method includes patterning a substrate with a substantially arbitrary arrangement of features by introducing irregularity into a repeating array of features.
    Type: Application
    Filed: September 20, 2005
    Publication date: January 26, 2006
    Inventor: Yan Borodovsky
  • Publication number: 20060017901
    Abstract: Systems and techniques for alignment with latent images. In one implementation, a method includes detecting a location of a latent image on a substrate, repositioning the substrate based on the detected location of the latent image, and patterning the substrate.
    Type: Application
    Filed: July 20, 2004
    Publication date: January 26, 2006
    Inventors: Yan Borodovsky, Ilya Grodnensky
  • Publication number: 20050255388
    Abstract: Systems and techniques for lithography. In one aspect, a method includes producing a microelectronic device by modulating an intensity and a phase of the zero diffraction order of a radiation with a device including subwavelength features having a pitch dimension smaller than one wavelength of the radiation.
    Type: Application
    Filed: May 14, 2004
    Publication date: November 17, 2005
    Inventors: Edita Tejnil, Yan Borodovsky
  • Publication number: 20050088633
    Abstract: A composite patterning technique may include two lithography processes. A first lithography process may use interference lithography to form an interference pattern of lines of substantially equal width and spaces on a photoresist. A second lithography process may use one or more non-interference lithography techniques, such as optical lithography, imprint lithography and electron-beam lithography, to break continuity of the patterned lines and form desired integrated circuit features.
    Type: Application
    Filed: October 24, 2003
    Publication date: April 28, 2005
    Inventor: Yan Borodovsky
  • Publication number: 20050085085
    Abstract: Systems and techniques for printing substrates. In one implementation, a method includes patterning a substrate with a substantially arbitrary arrangement of features by introducing irregularity into an array of repeating lines and spaces between the lines.
    Type: Application
    Filed: October 17, 2003
    Publication date: April 21, 2005
    Inventor: Yan Borodovsky
  • Publication number: 20050083497
    Abstract: Systems and techniques for printing substrates. In one implementation, a method includes patterning a substrate with a substantially arbitrary arrangement of features by introducing irregularity into a repeating array of features.
    Type: Application
    Filed: October 17, 2003
    Publication date: April 21, 2005
    Inventor: Yan Borodovsky
  • Publication number: 20050074698
    Abstract: A composite patterning technique may include three lithography processes. A first lithography process forms a periodic pattern of alternating continuous lines of substantially equal width and spaces on a first photoresist. A second lithography process uses a non-interference lithography technique to break continuity of the patterned lines and form portions of desired integrated circuit features. The first photoresist may be developed. A second photoresist is formed over the first photoresist. A third lithography process uses a non-interference lithography technique to expose a pattern on the second photoresist and form remaining desired features of an integrated circuit pattern.
    Type: Application
    Filed: October 7, 2003
    Publication date: April 7, 2005
    Inventor: Yan Borodovsky
  • Publication number: 20050073671
    Abstract: A composite patterning technique may include two lithography processes. A first lithography process may use interference lithography to form a continuous pattern of lines of substantially equal width on a photoresist. A second lithography process may use one or more non-interference lithography techniques, such as optical lithography, imprint lithography and electron-beam lithography, to break continuity of the patterned lines and form desired integrated circuit features.
    Type: Application
    Filed: October 7, 2003
    Publication date: April 7, 2005
    Inventor: Yan Borodovsky
  • Patent number: 6069739
    Abstract: A technique for introducing variable phase delay across portions of a spatially coherent light beam, such as a laser, without changing the focal length of the portions of the beam. A fly's-eye lens array is utilized to distribute the light for a more uniform illumination, but different length air gaps are introduced in the lens elements to provide a variable delay of portions of the beam. In a second scheme, a set of prisms is positioned in the path of the laser beam, in which the shape of the prism introduces variable phase delay across the cross-section of the beam.
    Type: Grant
    Filed: June 30, 1998
    Date of Patent: May 30, 2000
    Assignee: Intel Corporation
    Inventors: Yan Borodovsky, Christof Krautschik