Patents by Inventor Yan Lu

Yan Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240088309
    Abstract: A semiconductor device is provided. The semiconductor device includes a waveguide over a first dielectric layer. A first portion of the waveguide has a first width and a second portion of the waveguide has a second width larger than the first width. The semiconductor device includes a first doped semiconductor structure and a second doped semiconductor structure. The second portion of the waveguide is between the first doped semiconductor structure and the second doped semiconductor structure.
    Type: Application
    Filed: November 21, 2023
    Publication date: March 14, 2024
    Inventors: Chih-Tsung SHIH, Felix TSUI, Stefan RUSU, Chewn-Pu JOU, Hau-Yan LU
  • Patent number: 11928132
    Abstract: Provided are a database processing method and apparatus, and a computer readable storage medium. The database processing method comprises: after a lock wait is generated, writing lock wait related information into a lock wait log.
    Type: Grant
    Filed: April 21, 2020
    Date of Patent: March 12, 2024
    Assignee: XI'AN ZHONGXING NEW SOFTWARE CO., LTD.
    Inventors: Pin Lin, Yan Ding, Qinyuan Lu, Chen Qi, Yifang Yu, Pei Zhao
  • Patent number: 11928089
    Abstract: A data processing method includes: after receiving an export request for exporting data from the distributed database, acquiring, by a database import and export management node an active transaction list and export table distribution information at a current moment; notifying, by the database import and export management node, a corresponding database that the corresponding database performs a data export operation according to the export table distribution information; after determining that the corresponding database completes the data export operation, sending, by the database import and export management node, the active transaction list to a database agent node of the corresponding database; and after receiving a data consistency reverse compensation statement returned by the database agent node, importing, by the database import and export management node, the data exported by the corresponding database into a predetermined database and instructing the predetermined database to execute the data consist
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: March 12, 2024
    Assignee: ZTE CORPORATION
    Inventors: Longbo Guo, Yan Ding, Yiliang Xu, Peng Zhang, Jiashun Lu
  • Publication number: 20240079054
    Abstract: Methods for input/output voltage training of a three-dimensional (3D) memory device is disclosed. The method can comprise the following operations: (1) setting a reference voltage value at an on-die termination (ODT) enabled status; (2) controlling the 3D memory device to perform a write training process; (3) determining whether a further write training process is needed; (4) in response to determining that the further write training process is needed, repeating operations (1), (2) and (3); and (5) in response to determining that the further write training process is not needed, setting the reference voltage value as an optimized reference voltage value.
    Type: Application
    Filed: September 2, 2022
    Publication date: March 7, 2024
    Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Shiyang YANG, Chunfei Deng, Yan Lu, Ling Ding, Xiang Fu
  • Patent number: 11924178
    Abstract: Disclosed is a system and a method for information distribution. The system comprises: a server for generating a group key and its corresponding key deriving parameter, wherein the server encrypts sensitive contents by using the group key to obtain encrypted information; and terminals configured to receive the encrypted information through an open channel, extract the group key, then decrypt the encrypted information by using the group key to obtain the original content. In the group forming process, each terminal encrypts its private identifier using the public key and submits the ciphertext to the server. In information distribution process, the server transmits the ciphertext of sensitive contents and the key deriving parameter to the terminals via open channel Because private information available only to respective group members is required for calculating the group key, this mechanism ensures that the sensitive content can be transmitted securely on the open channel.
    Type: Grant
    Filed: December 13, 2021
    Date of Patent: March 5, 2024
    Assignee: MAXIO Technology (Hangzhou) Co., Ltd.
    Inventors: Gang Fang, Wei Xu, Yan Cai, Jun Chen, Zhehang Wen, Li Liang, Guohua Chen, Yiming Lu
  • Patent number: 11920932
    Abstract: A wafer-level assembly method for a micro hemispherical resonator gyroscope includes: after independently manufactured glass substrates are softened and deformed at a high temperature, forming a micro hemispherical resonator on the glass substrate; forming glass substrate alignment holes at both ends of the glass substrate by laser ablation; aligning and fixing a plurality of identical micro hemispherical resonators on a wafer fixture by using the alignment holes as a reference, and then performing operations by using the wafer fixture as a unit to implement subsequent processes that include: releasing the micro hemispherical resonators, metallizing the surface, fixing to the planar electrode substrates, separating the wafer fixture and cleaning to obtain a micro hemispherical resonator gyroscope driven by a bottom planar electrode substrate.
    Type: Grant
    Filed: September 17, 2020
    Date of Patent: March 5, 2024
    Assignee: NATIONAL UNIVERSITY OF DEFENSE TECHNOLOGY
    Inventors: Xuezhong Wu, Dingbang Xiao, Xiang Xi, Yulie Wu, Hanhui He, Yan Shi, Kun Lu, Bin Li, Yimo Chen, Chao Yuan, Bao Nie
  • Publication number: 20240067608
    Abstract: The application describes methods for making a deuterated dextromethorphan of Formula (I), deuterated dextromethorphan produced by these methods, and pharmaceutically acceptable salts thereof.
    Type: Application
    Filed: November 8, 2023
    Publication date: February 29, 2024
    Inventors: Matt Johnson, Cunxiang Zhao, Weihua Meng, Zhijun Lu, Yan Li
  • Publication number: 20240073100
    Abstract: Disclosed are an isolation method for a high-performance computer system, and a high-performance computer system. The isolation method comprises node-level isolation performed. The node-level isolation comprises: configuring a routing table for each computing node, and configuring, in the routing table, valid routing information for computing node pairs; when any one source computing node needs to communicate with a target computing node, determining, by lookup, whether valid routing information exists between the source computing node and the target computing node according to the configured routing table; if so, allowing the source computing node to communicate with the target computing node; otherwise, forbidding the source computing node from communicating with the target computing node.
    Type: Application
    Filed: June 27, 2023
    Publication date: February 29, 2024
    Applicant: NATIONAL UNIVERSITY OF DEFENSE TECHNOLOGY
    Inventors: Pingjing LU, Mingche LAI, Zeyu XIONG, Jinbo XU, Junsheng CHANG, Xingyun QI, Zhang LUO, Yuan LI, Yan SUN, Yang OU, Zicong WANG, Jianmin ZHANG
  • Publication number: 20240071530
    Abstract: A program operation is initiated to program a set of target memory cells of a target wordline of a memory device to a target programming level. During a program verify operation of the program operation, a program verify voltage level is caused to be applied to the target wordline to verify programming of the set of target memory cells. A pass through read voltage level associated with the target wordline is identified. During the program verify operation, a pass through voltage level is caused to be applied to at least one of a first wordline or a second wordline, wherein the pass through read voltage level is the read voltage level reduced by an offset value.
    Type: Application
    Filed: August 14, 2023
    Publication date: February 29, 2024
    Inventors: Ching-Huang Lu, Hong-Yan Chen, Yingda Dong
  • Patent number: 11917213
    Abstract: This application provides a live streaming processing method performed by an electronic device. The method includes: displaying a live streaming room, the live stream room having a host account, a host sub-account and multiple viewer accounts, the host sub-account being used for assisting the host account of the live streaming room in operation; receiving real-time live streaming data of the live streaming room, and displaying a live streaming content on a live streaming room page according to the real-time live streaming data, the real-time live streaming data collected from the host account and the viewer accounts; and displaying, in response to a live streaming room operation of the host sub-account, an operation result of the live streaming room operation of the host sub-account in the live streaming room, wherein the operation result of the live streaming room operation updates the live streaming content on the live streaming room page.
    Type: Grant
    Filed: September 19, 2022
    Date of Patent: February 27, 2024
    Assignee: TENCENT TECHNOLOGY (SHENZHEN) COMPANY LIMITED
    Inventors: Longqi Ding, Di Chen, Shuyou Li, Hengkai Wan, Junqiu Lu, Yan Long, Fenglian Wei, Ting Huang
  • Patent number: 11912729
    Abstract: Provided are a boron-silicon heterocyclic compound having a structure represented by formula 1, a display device and a display apparatus. In formula 1, L1 and L2 are each a single bond, C6-C30 arylene, C6-C30 fused arylene, C4-C30 heteroarylene, or C4-C30 fused heteroarylene; D1 and D2 are each a substituted or unsubstituted C6-C60 aryl, a substituted or unsubstituted C4-C60 heteroaryl, a substituted or unsubstituted C10-C60 fused aryl, a substituted or unsubstituted C8-C30 fused heteroaryl, or a substituted or unsubstituted diphenylamino. The compound has a strong inductive effect and can reduce the driving voltage of the device. The silacyclopentadiene having a silicon atom as spiro-atom can effectively improve the solubility of the material, which is beneficial to the cleaning of the vapor deposition mask. In addition, the compound has a higher triplet energy level to effectively transfer energy to the luminous body, and improves the efficiency of the device.
    Type: Grant
    Filed: August 26, 2020
    Date of Patent: February 27, 2024
    Assignees: WUHAN TIANMA MICRO-ELECTRONICS CO., LTD., WUHAN TIANMA MICROELECTRONICS CO., LTD. SHANGHAI BRANCH
    Inventors: Lei Zhang, Wei Gao, Jinghua Niu, Ying Liu, Dongyang Deng, Yan Lu, Hongyan Zhu, Xia Li
  • Publication number: 20240045143
    Abstract: An optical waveguide structure of a semiconductor photonic device includes a first semiconductor waveguide, a second semiconductor waveguide, and an air seam between the first and second semiconductor waveguides. The semiconductor waveguides extend in a first direction, and a plurality of air seams extend in a second direction. Each of the air seams is disposed between two adjacent semiconductor waveguides. A distance between the two adjacent semiconductor waveguides is less than a width of each semiconductor waveguide.
    Type: Application
    Filed: August 3, 2022
    Publication date: February 8, 2024
    Inventors: CHIH-TSUNG SHIH, HAU-YAN LU, WEI-KANG LIU, YINGKIT FELIX TSUI
  • Patent number: 11892681
    Abstract: A coupling system includes an optical fiber configured to carry an optical signal. The coupling system further includes a chip in optical communication with the optical fiber. The chip includes a substrate. The chip further includes a grating on a first side of the substrate, wherein the grating is configured to receive the optical signal. The chip further includes an interconnect structure over the grating on the first side of the substrate, wherein the interconnect structure defines a cavity aligned with the grating. The chip further includes a first polysilicon layer on a second side of the substrate, wherein the second side of the substrate is opposite to the first side of the substrate.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: February 6, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen-Hao Huang, Hau-Yan Lu, Sui-Ying Hsu, Yuehying Lee, Chien-Ying Wu, Chien-Chang Lee, Chia-Ping Lai
  • Publication number: 20240019639
    Abstract: An edge coupler, a waveguide structure and a method for forming a waveguide structure are provided. The edge coupler includes a substrate, a first cladding layer, a core layer and a first anti-reflection coating layer. The first cladding layer has a second sidewall aligned with a first sidewall of the substrate. The core layer has a third sidewall aligned with the second sidewall. The anti-reflection coating layer lines the first sidewall, the second sidewall and the third sidewall. A thickness of the anti-reflection coating layer varies along the first sidewall, the second sidewall and the third sidewall.
    Type: Application
    Filed: July 13, 2022
    Publication date: January 18, 2024
    Inventors: WEI-KANG LIU, CHIH-TSUNG SHIH, HAU-YAN LU, YINGKIT FELIX TSUI
  • Publication number: 20240012199
    Abstract: Some implementations described herein include a photonics integrated circuit device including a photonics structure. The photonics structure includes a waveguide structure and an optical attenuator structure. In some implementation, the optical attenuator structure is formed on an end region of the waveguide structure and includes a metal material or a doped material. In some implementations, the optical attenuator structure includes a gaussian doping profile within a portion of the waveguide structure. The optical attenuator structure may absorb electromagnetic waves at the end of the waveguide structure with an efficiency that is improved relative to a spiral optical attenuator structure or metal cap optical attenuator structure.
    Type: Application
    Filed: July 8, 2022
    Publication date: January 11, 2024
    Inventors: Wei-kang LIU, Chih-Tsung SHIH, Hau-Yan LU, YingKit Felix TSUI, Lee-Shian JENG
  • Patent number: 11869991
    Abstract: A semiconductor device is provided. The semiconductor device includes a waveguide over a first dielectric layer. A first portion of the waveguide has a first width and a second portion of the waveguide has a second width larger than the first width. The semiconductor device includes a first doped semiconductor structure and a second doped semiconductor structure. The second portion of the waveguide is between the first doped semiconductor structure and the second doped semiconductor structure.
    Type: Grant
    Filed: March 2, 2021
    Date of Patent: January 9, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Chih-Tsung Shih, Hau-Yan Lu, Felix Tsui, Stefan Rusu, Chewn-Pu Jou
  • Publication number: 20240004131
    Abstract: A semiconductor structure includes a waveguide and an optical attenuator. The waveguide is disposed over an insulating layer and configured to guide light. The optical attenuator is connected to the waveguide. The optical attenuator has a first surface and a second surface opposite the first surface, and a cross-sectional width of the optical attenuator decreases from the first surface to the second surface.
    Type: Application
    Filed: July 1, 2022
    Publication date: January 4, 2024
    Inventors: WEI-KANG LIU, LEE-SHIAN JENG, CHIH-TSUNG SHIH, HAU-YAN LU, YINGKIT FELIX TSUI
  • Patent number: 11858549
    Abstract: A method for generating a steering command for controlling a vehicle is provided.
    Type: Grant
    Filed: November 9, 2020
    Date of Patent: January 2, 2024
    Assignee: GM GLOBAL TECHNOLOGY OPERATIONS LLC
    Inventors: Amir Takhmar, Joshua M. Levin, Jimmy Zhong Yan Lu, Jayant Sachdev, Reza Zarringhalam
  • Patent number: 11855089
    Abstract: A semiconductor device includes a silicon substrate; a semiconductor fin over the silicon substrate; and an isolation structure over the silicon substrate. The semiconductor fin includes a first portion and a second portion over the first portion. The first portion is surrounded by the isolation structure, and the second portion protrudes above the isolation structure. The second portion has a different crystalline lattice constant than the first portion. The first portion includes a first dopant, and the second portion is substantially free of the first dopant. The semiconductor device further includes a gate structure above the isolation structure and engaging multiple surfaces of the second portion.
    Type: Grant
    Filed: June 8, 2022
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yong-Yan Lu, Chia-Wei Soong, Hou-Yu Chen
  • Patent number: 11848390
    Abstract: At least one doped silicon region is formed in a silicon layer of a semiconductor substrate, and a silicon oxide layer is formed over the silicon layer. A germanium-containing material portion is formed in the semiconductor substrate to provide a p-n junction or a p-i-n junction including the germanium-containing material portion and one of the at least one doped silicon region. A capping material layer that is free of germanium is formed over the germanium-containing material portion. A first dielectric material layer is formed over the silicon oxide layer and the capping material layer. The first dielectric material layer includes a mesa region that is raised from the germanium-containing material portion by a thickness of the capping material layer. The capping material layer may be a silicon capping layer, or may be subsequently removed to form a cavity. Dark current is reduced for the germanium-containing material portion.
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: December 19, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chen-Hao Huang, Hau-Yan Lu, Sui-Ying Hsu, YuehYing Lee, Chien-Ying Wu, Chia-Ping Lai