Patents by Inventor Yan Lu

Yan Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230138038
    Abstract: Disclosed in some examples are methods, systems, and machine-readable mediums which determine jitter buffer delay by inputting jitter buffer and currently observed network status information to a machine learned model that is trained using a reinforcement learning (RL) method. The model maps these inputs to an action to compress, stretch, or hold the jitter buffer delay, which is used by a recipient computing device to optimize the jitter buffer delay. The model may be trained using a simulator that uses network traces of past real streaming sessions (e.g., communication sessions) of users. By training the model through reinforcement learning, the model learns to make better decisions through reinforcement in the form of reward signals that reflect the performance of each decision.
    Type: Application
    Filed: December 30, 2022
    Publication date: May 4, 2023
    Inventors: Xiulian Peng, Vinod Prakash, Xiangyu Kong, Sriram Srinivasan, Yan Lu
  • Publication number: 20230114417
    Abstract: Steel for glass lining, comprising the following chemical elements in mass percent: C: 0.015-0.060%, Si: 0.01-0.50%, Mn: 0.20-1.5%, P: 0.005-0.10%, Al: 0.010-0.070%, Ti: 0.10-0.30%, and the balance of Fe and other inevitable impurities. The microstructure of the steel for glass lining is a ferrite or a combination of a ferrite and a cementite. In addition, also disclosed is a production method for steel for glass lining, comprising the steps of (1) smelting, refining, and continuous casting to obtain a slab; (2) heating, the heating temperature being 1050-1250° C.; (3) hot rolling, the final temperature of hot rolling being controlled to be 800-920° C.; (4) cooling; and (5) thermal treatment. The steel for glass lining has excellent machinability and low temperature toughness, and also has excellent lining performance.
    Type: Application
    Filed: February 23, 2021
    Publication date: April 13, 2023
    Applicant: BAOSHAN IRON & STEEL CO., LTD.
    Inventors: Quanshe SUN, Shijie YAO, Yan LU, Junkai WANG, Qin QIN
  • Patent number: 11625521
    Abstract: A method for debugging a logic system design including a target module to be debugged. The method includes receiving a first gate-level netlist associated with the logic system design and a second gate-level netlist associated with the target module that are generated based on a description of the logic system design, obtaining runtime information of an input signal of the target module by running the first gate-level netlist, and obtaining runtime information of the target module by running the second gate-level netlist based on the runtime information of the input signal of the target module.
    Type: Grant
    Filed: September 2, 2021
    Date of Patent: April 11, 2023
    Assignee: XEPIC CORPORATION LIMITED
    Inventor: Yan Lu
  • Patent number: 11622875
    Abstract: An intestinal barrier sleeve release system includes a tubular housing having a first opening at one end and a second opening at the other end. A tubular sleeve to be released is disposed in the housing. A release body connected to the one end of the tubular sleeve is disposed at the first opening of the housing and is made of a material that can be dissolved and absorbed in human intestines. An inner sheath, a middle sheath and an outer sheath are sequentially set and move relative to each other. The inner sheath and the middle sheath are operated to move axially, the release body is disengaged from the housing, and the tubular sleeve moves out of the housing and is released at a specified position of the human intestines.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: April 11, 2023
    Assignee: HANGZHOU TANGJI MEDICAL TECHNOLOGY CO., LTD.
    Inventors: Yuxing Zuo, Yan Lu
  • Patent number: 11623926
    Abstract: The present disclosure describes an electroluminescent material which is formed of a compound having a structure of Formula (I), an OLED display panel utilizing the compound and an electronic device having the OLED display panel. The OLED display panel includes a first electrode, a second electrode, and an organic thin film layer disposed between the first electrode and the second electrode. The organic thin film layer comprises an electron transport layer which comprises any one or a combination of at least two of the compounds. The electroluminescent material has a triplet energy level ET of ?2.7 eV, a HOMO energy level of ??5.85 eV, and a glass transition temperature of >120° C. This compound improves luminous efficiency in the OLED display panel and the electronic device.
    Type: Grant
    Filed: December 31, 2019
    Date of Patent: April 11, 2023
    Assignee: WUHAN TIANMA MICROELECTRONICS CO., LTD. SHANGHAI BRANCH
    Inventors: Lei Zhang, Wei Gao, Jinghua Niu, Wenpeng Dai, Yan Lu, Yang Li, Ying Liu
  • Publication number: 20230108645
    Abstract: Innovations in adaptive encoding of screen content based on motion type are described. For example, a video encoder system receives a current picture of a video sequence. The video encoder system determines a current motion type for the video sequence and, based at least in part on the current motion type, sets one or more encoding parameters. Then, the video encoder system encodes the current picture according to the encoding parameter(s). The innovations can be used in real-time encoding scenarios when encoding screen content for a screen sharing application, desktop conferencing application, or other application. In some cases, the innovations allow a video encoder system to adapt compression to different characteristics of screen content at different times within the same video sequence.
    Type: Application
    Filed: October 1, 2021
    Publication date: April 6, 2023
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Satya Sasikanth BENDAPUDI, Ming-Chieh LEE, Yan LU, Bin LI, Jizhe JIN, Jiahao LI, Shao-Ting WANG
  • Publication number: 20230108722
    Abstract: Innovations in allocation of bit rate between video streams using machine learning are described. For example, a controller of a video encoder system receives first feedback values that indicate results of encoding part of a first video sequence (e.g., screen content). The controller also receives second feedback values that indicate results of encoding part of a second video sequence (e.g., camera video content). A machine learning model accepts, as inputs, the first feedback values and second feedback values. The machine learning model produces, as output, a reallocation parameter. The controller determines a first target bit rate and a second target bit rate using the reallocation parameter. A first video encoder encodes one or more pictures of the first video sequence at the first target bit rate, and a second video encoder encodes one or more pictures of the second video sequence at the second target bit rate.
    Type: Application
    Filed: October 1, 2021
    Publication date: April 6, 2023
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Satya Sasikanth BENDAPUDI, Ming-Chieh LEE, Yan LU, Bin LI, Jiahao LI
  • Patent number: 11622118
    Abstract: Techniques are described for efficiently encoding video data by skipping evaluation of certain encoding modes based on various evaluation criteria. In some solutions, intra-block evaluation is performed in a specific order during encoding, and depending on encoding cost calculations of potential intra-block encoding modes, evaluation of some of the potential modes can be skipped. In some solutions, some encoding modes can be skipped depending on whether blocks are simple (e.g., simple vertical, simple horizontal, or both) or non-simple. In some solutions, various criteria are applied to determine whether chroma-from-luma mode evaluation can be skipped. The various solutions can be used independently and/or in combination.
    Type: Grant
    Filed: November 9, 2021
    Date of Patent: April 4, 2023
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Thomas W. Holcomb, Jiahao Li, Bin Li, Yan Lu, Mei-Hsuan Lu, Andrey Mikhaylovic Mezentsev, Ming-Chieh Lee
  • Patent number: 11610192
    Abstract: Systems and methods for predicting language dialects for a user to improve a user interface of an application are disclosed. In one embodiment, a system receives a request to determine a default dialect for an application executing on a user device. The system acquires user information corresponding to a user of the user device. Based on the user information and using a clustering algorithm, the system assigns the user to a cluster associated with a dialect. The system provides the dialect to the user device for display in a user interface as part of a sliding scale of selectable dialects of the application such that the dialect is provided as the default dialect for text and other message communications in the application. The system learns from the user's choice of dialect to provide more accurate dialect predictions in the future for other users.
    Type: Grant
    Filed: September 21, 2020
    Date of Patent: March 21, 2023
    Assignee: PayPal, Inc.
    Inventors: Aarti Ashok, Michael George McKenna, Girish Maheswarappa Halavarthi, Joelle Cheng, Sine Rix, Sung-Yan Lu, Gulrez Khan, Lucas Welti
  • Publication number: 20230069212
    Abstract: An optical integrated circuit (IC) structure includes: a substrate including a fiber slot formed in an upper surface of the substrate and extending from an edge of the substrate, and an undercut formed in the upper surface and extending from the fiber slot; a semiconductor layer disposed on the substrate; a dielectric structure disposed on the semiconductor layer; an interconnect structure disposed in the dielectric structure; a plurality of vents that extend through a coupling region of the dielectric structure and expose the undercut; a fiber cavity that extends through the coupling region of dielectric structure and exposes the fiber slot; and a barrier ring disposed in the dielectric structure, the barrier ring surrounding the interconnect structure and routed around the perimeter of the coupling region.
    Type: Application
    Filed: August 30, 2021
    Publication date: March 2, 2023
    Inventors: Chen-Hao HUANG, Hau-Yan Lu, Sui-Ying Hsu, Yuehying Lee, Chien-Ying Wu, Chia-Ping Lai
  • Publication number: 20230061940
    Abstract: A coupling system includes an optical fiber configured to carry an optical signal. The coupling system further includes a chip in optical communication with the optical fiber. The chip includes a substrate. The chip further includes a grating on a first side of the substrate, wherein the grating is configured to receive the optical signal. The chip further includes an interconnect structure over the grating on the first side of the substrate, wherein the interconnect structure defines a cavity aligned with the grating. The chip further includes a first polysilicon layer on a second side of the substrate, wherein the second side of the substrate is opposite to the first side of the substrate.
    Type: Application
    Filed: August 27, 2021
    Publication date: March 2, 2023
    Inventors: Chen-Hao HUANG, Hau-Yan LU, Sui-Ying HSU, Yuehying LEE, Chien-Ying WU, Chien-Chang LEE, Chia-Ping LAI
  • Patent number: 11582859
    Abstract: A method for manufacturing a flexible circuit board capable of transmitting high frequency signals with reduced attenuation includes providing an inner wiring board including a first conductive wiring layer and a first substrate layer, the first conductive wiring layer including a signal line and two ground lines on both sides of the signal line, the first substrate layer covering a side of the first conductive wiring layer and defining first through holes which expose the signal line; providing two copper clad laminates including a second substrate layer and a copper foil, the second substrate layer having second through hole aligned with the first through holes; laminating the two copper clad laminates onto two sides of the inner wiring board via two adhesive layers, each adhesive layer defining third through holes aligned with the first and second through holes; and forming a second conductive wiring layer from the copper foil.
    Type: Grant
    Filed: September 6, 2021
    Date of Patent: February 14, 2023
    Assignees: HongQiSheng Precision Electronics (QinHuangDao) Co., Ltd., Avary Holding (Shenzhen) Co., Limited.
    Inventors: Bao-Jun Li, Yang Li, Yan-Lu Li, Li-Kun Liu
  • Patent number: 11574907
    Abstract: A semiconductor device includes a substrate, a fin structure and an isolation layer formed on the substrate and adjacent to the fin structure. The semiconductor device includes a gate structure formed on at least a portion of the fin structure and the isolation layer. The semiconductor device includes an epitaxial layer including a strained material that provides stress to a channel region of the fin structure. The epitaxial layer has a first region and a second region, in which the first region has a first doping concentration of a first doping agent and the second region has a second doping concentration of a second doping agent. The first doping concentration is greater than the second doping concentration. The epitaxial layer is doped by ion implantation using phosphorous dimer.
    Type: Grant
    Filed: February 8, 2021
    Date of Patent: February 7, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Chang Lin, Chun-Feng Nieh, Huicheng Chang, Hou-Yu Chen, Yong-Yan Lu
  • Patent number: 11575089
    Abstract: The present disclosure belongs to the technical field of organic light-emitting diods (OLEDs), and provides a compound used as an electron transmission material of OLEDs. Molecules of the compounds include an aromatic ring (or aromatic fused ring) and a phenanthroline group that are connected to each other. In an embodiment, the compound according to the present disclosure includes two types of groups, i.e., an aromatic ring (or aromatic fused ring) and a phenanthroline (or benzoquinoline) group. These two groups not only have good electron accepting ability, but also can be well doped with metals. The planarity of the two groups is conducive to the stacking of molecules, which facilitates the combination of holes and electrons and generates excitons, thereby increasing the electron mobility of the material and improving efficiency of device.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: February 7, 2023
    Assignees: WUHAN TIANMA MICROELECTRONICS CO., LTD., Wuhan Tianma Microelectronics Co., Ltd. Shanghai Branch
    Inventors: Lei Zhang, Wei Gao, Jinghua Niu, Wenpeng Dai, Yan Lu
  • Patent number: 11569230
    Abstract: A method for forming a semiconductor device comprises receiving a structure having a substrate, an isolation structure over the substrate, and a fin over the substrate and adjacent to the isolation structure. The method further includes etching a portion of the fin, resulting in a trench, forming a doped material layer over bottom and sidewalls of the trench, and growing at least one epitaxial layer over the doped material layer in the trench. The method further includes recessing the isolation structure and the doped material layer, leaving a first portion of the at least one epitaxial layer surrounded by the doped material layer and performing an annealing process, thereby driving dopants from the doped material layer into the first portion.
    Type: Grant
    Filed: October 5, 2020
    Date of Patent: January 31, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yong-Yan Lu, Chia-Wei Soong, Hou-Yu Chen
  • Patent number: 11558275
    Abstract: Disclosed in some examples are methods, systems, and machine-readable mediums which determine jitter buffer delay by inputting jitter buffer and currently observed network status information to a machine learned model that is trained using a reinforcement learning (RL) method. The model maps these inputs to an action to compress, stretch, or hold the jitter buffer delay, which is used by a recipient computing device to optimize the jitter buffer delay. The model may be trained using a simulator that uses network traces of past real streaming sessions (e.g., communication sessions) of users. By training the model through reinforcement learning, the model learns to make better decisions through reinforcement in the form of reward signals that reflect the performance of each decision.
    Type: Grant
    Filed: May 18, 2020
    Date of Patent: January 17, 2023
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Xiulian Peng, Vinod Prakash, Xiangyu Kong, Sriram Srinivasan, Yan Lu
  • Patent number: 11551027
    Abstract: Implementations of the subject matter described herein relate to object detection based on deep neural network. With a given input image, it is desired to determine a class and a boundary of one or more objects within the input image. Specifically, a plurality of channel groups is generated from a feature map of an image, the image including at least a region corresponding to a first grid. A target feature map is extracted from at least one of the plurality of channel groups associated with a cell of the first grid. Information related to an object within the region is determined based on the target feature map. The information related to the object may be a class and/or a boundary of the object.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: January 10, 2023
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Jingjing Fu, Yao Zhai, Yan Lu
  • Patent number: 11532759
    Abstract: At least one doped silicon region is formed in a silicon layer of a semiconductor substrate, and a silicon oxide layer is formed over the silicon layer. A germanium-containing material portion is formed in the semiconductor substrate to provide a p-n junction or a p-i-n junction including the germanium-containing material portion and one of the at least one doped silicon region. A capping material layer that is free of germanium is formed over the germanium-containing material portion. A first dielectric material layer is formed over the silicon oxide layer and the capping material layer. The first dielectric material layer includes a mesa region that is raised from the germanium-containing material portion by a thickness of the capping material layer. The capping material layer may be a silicon capping layer, or may be subsequently removed to form a cavity. Dark current is reduced for the germanium-containing material portion.
    Type: Grant
    Filed: January 27, 2021
    Date of Patent: December 20, 2022
    Inventors: Chen-Hao Huang, Hau-Yan Lu, Sui-Ying Hsu, Yuehying Lee, Chien-Ying Wu, Chia-Ping Lai
  • Patent number: 11517461
    Abstract: A gastric diverter and a digestive tract support and a release method thereof. The digestive tract support has undeployed shape and deployed shape, and includes upper support, lower support and connecting member. In the deployed shape, a first opening is provided at top of the upper support, a second opening is provided at bottom thereof, and the lower support is disposed below the upper support; a third opening is provided at top of the lower support, a fourth opening is provided at bottom thereof, and the upper support and the lower support are connected by a plurality of connecting members; the fourth opening of the lower support is connected to a membrane tube, the deployed upper support and lower support both cannot pass through an open gastric pyloric orifice, and the connecting members can pass through the gastric pyloric orifice or be placed at the gastric pyloric orifice.
    Type: Grant
    Filed: October 24, 2018
    Date of Patent: December 6, 2022
    Assignee: HANGZHOU TANGJI MEDICAL TECHNOLOGY CO. LTD
    Inventors: Yuxing Zuo, Yan Lu
  • Patent number: 11508658
    Abstract: The present disclosure provides a semiconductor device package. The semiconductor device package includes a semiconductor substrate having a first surface and a first optical coupler disposed on the first surface of the semiconductor substrate. The first optical coupler includes a first surface facing away from the first surface of the semiconductor substrate and a first lateral surface connected to the first surface of the first optical coupler. The first surface of the first optical coupler and the first lateral surface of the optical coupler define an angle greater than 90 degrees. A method of manufacturing a semiconductor device package is also disclosed.
    Type: Grant
    Filed: April 1, 2020
    Date of Patent: November 22, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hau-Yan Lu, Felix Ying-Kit Tsui, Jing-Hwang Yang, Feng Yuan