Abstract: In order to reduce a test time for a synchronous type memory device, a compression circuit compresses a plurality of memory cell data which are inputted in a plurality of read registers provided for a data output terminal to 1-bit data. A bank selection circuit selects an output of the compression circuit of either a bank #A or a bank #B. A tristate inverter buffer passes the 1-bit compression data selected by the bank selection circuit in accordance with a test mode command signal. The data output terminal outputs compressed data of a plurality of bits of memory cells. Thus, it is possible to simultaneously determine pass/fail of a plurality of memory cells, thereby reducing the test time.

Abstract: A DRAM includes an N-type well formed on a main surface of a P-type semiconductor substrate, an N-type impurity region formed on the main surface of the P-type semiconductor substrate, a P-type impurity region formed in the N-type well to be a storage node of a memory capacitor, and a polycrystalline silicon layer for connecting the P-type impurity region and the N-type impurity region. The N-type impurity layer, the P-type impurity layer, and the polycrystalline silicon layer constitute the storage node of the memory capacitor, and electrons of minority carriers flowing from the substrate to the N-type impurity layer are recombined with holes flowing from the N-type well to the P-type impurity layer.

Abstract: A synchronous semiconductor memory device includes an automatic refresh detection circuit for detecting that an automatic refresh mode is specified in accordance with an automatic refresh command, an address counter for generating a refresh address, a refresh execution unit for refreshing a memory array in accordance with an automatic refresh detection signal and the refresh address, an inactivation circuit for inactivating the refresh execution unit after a lapse of a prescribed time in accordance with the automatic refresh detection signal, a counter check mode detection circuit for bringing the inactivation circuit into an inoperable state in accordance with a counter check mode command, and a second inactivation circuit for inactivating the refresh execution unit in accordance with a precharge detection signal generated in response to a precharge command. Thus synchronous semiconductor memory device with an operation mode which can test the function of an internal refresh address counter is provided.

Abstract: A first signal generation circuit generates a signal which rises from the ground level to a second level when a prescribed time elapses after an external supply potential starts to rise from the ground level to a first level. A second signal generation circuit outputs a power-on reset signal which falls when the signal outputted from the first signal generation circuit exceeds a first prescribed level and an internal supply potential for an internal circuit outputted from internal supply potential generation means exceeds a second prescribed level.

Abstract: In a synchronous semiconductor memory device, memory arrays (MA) forming activation units each are divided into a plurality of small memory arrays (MK). There are provided local I/O line pairs (LIO) each for two small memory arrays. The global I/O line pairs (GIO) crossing word lines are arranged in word line shunt regions (WS). The connection switches (BS) are arranged in the crossing between the local I/O line pairs and global I/O line pairs. Each small memory array in the activated memory array is connected to the corresponding global I/O line pair through the local I/O line pair. Thereby, a plurality of bits can be simultaneously read without increasing an area occupied by interconnections. The control of connection switch is made using a sense amplifier activation signal. Global I/O lines are precharged/equalized after data are transferred to read data registers provided for data output terminal for sequential data output or into selected memory cells.

Abstract: Memory arrays are divided into banks which can be operated independent from each other. Read data storing registers and write data storing registers operating independent from each other are provided for the banks. The memory array is divided into a plurality of small array blocks, local IO lines are arranged corresponding to each array block, and the local IO lines are connected to global IO lines. The global IO lines are connected to preamplifier groups and to write buffer groups. By control signal generating circuits and by a register control circuit, inhibition of writing of a desired bit only during successive writing operation can be done, data can be collectively written to the selected memory cells when the final data is input if the data writing should be stopped before reaching the wrap length in successive writing, and the timing for activating the memory array when the write cycle should be repeatedly carried out can be delayed.

Abstract: A DRAM includes an N-type well formed on a main surface of a P-type semiconductor substrate, an N-type impurity region formed on the main surface of the P-type semiconductor substrate, a P-type impurity region formed in the N-type well to be a storage node of a memory capacitor, and a polycrystalline silicon layer for connecting the P-type impurity region and the N-type impurity region. The N-type impurity layer, the P-type impurity layer, and the polycrystalline silicon layer constitute the storage node of the memory capacitor, and electrons of minority carriers flowing from the substrate to the N-type impurity layer are recombined with holes flowing from the N-type well to the P-type impurity layer.

Abstract: In a DRAM of separated I/O type, column selecting lines for reading data and column selecting lines for writing data are provided independently from each other. An addition circuit is provided corresponding to each memory cell array block for precharging, when that memory cell array is not selected, a read line pair corresponding that memory cell array block to the same potential Vb1 as that of the bit lines equalized by an equalizer circuit. Both in data reading and writing operations, current does not flow between any equalizer circuit and the write data line pair provided corresponding to each unselected memory cell array block in spite of the fact that a transistor for write selection is not provided in each bit line pair.

Abstract: Disclosed is a DRAM including a test mode operation capable of testing whether a plurality of memory cells are defective or not in a short time. The DRAM includes a power-on detection signal generator, a power-on reset signal generator, and a test mode instruction signal generator. The power-on detection signal generator detects application of a power supply voltage and generates a power-on detection signal. The power-on reset signal generator is reset by a power-on reset signal, counts at least once an external RAS signal applied after reset and generates a power-on reset signal. The test mode instruction signal generator detects logic states of an internal RAS signal, an internal CAS signal and an internal W signal applied after the power-on reset and generates a test mode instructing signal.

Abstract: A dynamic-type semiconductor memory device has a test mode of simultaneously carrying out functional testing on a plurality of bits of memory cells. In data writing in the test mode, data inverted from the write-in data is written in at least a 1-bit memory cell out of the plurality of bits of memory cells selected simultaneously, and the same data as the write-in data is written in the remaining memory cells. In data reading in the test mode, the data of those of the memory cells selected simultaneously, in which the inverted data is written are inverted and read, while the data of the remaining memory cells are read as they are. Logic processing is carried out on the read-out data of the plurality of bits, so that a logic value indicating acceptability of the semiconductor memory device is output, depending on a result of determination as to whether or not the read-out data is the same as each other.

Abstract: A plurality of memory arrays (10a, 10b) are formed on a semiconductor chip (CH). A peripheral circuit (60) is arranged in the central portion of the plurality of memory arrays (10a, 10b). A plurality of pads (PD;p1.about.p18) are formed on both ends of the semiconductor chip (CH). The plurality of memory arrays (10a, 10b) are formed of predetermined layers (101.about.109). A plurality of interconnections (L) to be connected between the plurality of pads (PD;p1.about.p18) and the peripheral circuit (60) are provided to cross the plurality of memory arrays. The plurality of interconnections (L) are formed of layers (112;113) other than the predetermined ones.

Abstract: A residual charge removing circuit connected to a node in a power-on reset pulse generating circuit for removing positive charges which remain in this node when a power supply is turned off is disclosed. This residual charge removing circuit is formed of two N-channel MOS transistors connected in series between the node and the ground, and one capacitor. Out of the two N-channel MOS transistors, the transistor near the node has a grounded gate. The capacitor is connected between a gate of the transistor, out of the two N-channel MOS transistors, which is distant from the node, and a power supply. The gate of the transistor distant from the node is connected to a connection point between the two N-channel MOS transistors. Therefore, when a supply potential lowers below a threshold voltage Vth of the MOS transistors due to the power-off, the transistor distant from the node is turned off, so that a potential of the connection point becomes -Vth owing to a discharge of negative charges from the capacitor.

Abstract: A semiconductor memory device comprises eight memory arrays (b 10a, 10b) arranged in one column. A peripheral circuit (60) is arranged in the central portion of the eight memory arrays (10a, 10b), two column decoders (51, 52) being arranged with the peripheral circuit (60) interposed therebetween. Each of the eight memory arrays (10a, 10b) is provided with a row decoder (20). A plurality of first column selecting lines (CL1) are provided so as to cross the three memory arrays (10a, 10b) arranged on one side of the peripheral circuit (60) from the column decoder (51). In addition, a plurality of second column selecting lines (CL2) are provided so as to intersect with the three memory arrays (10a, 10b) arranged on the other side of the peripheral circuit (60) from the column decoder (52).

Abstract: A semiconductor dynamic RAM provided with an I/O load (5) rendered inactive during a writing cycle comprises a monostable multivibrator (16) for receiving a read/write indicating signal W for indicating reading and writing data from and into a memory cell (2) and outputting a signal We having a shorter duration than that of the signal W at down edge of the signal W as a trigger. The output signal We of the monostable multivibrator (16) is supplied as a control signal for rendering the I/O load (5) inactive.

Abstract: A memory cell array (10) is divided into four blocks. Each block comprises a memory cell array block (10aand a memory cell array block (10b). A sense amplifier block (20) is disposed between the memory cell array blocks (10a) and (10b). Each sense amplifier block (20) is connected to the memory cell array blocks (10a) and (10b) via switching circuits (80a, 80b), respectively. Four decoders (51) are provided corresponding to the four blocks. The four decoders (51) are commonly provided with a driver (52) generating a high level driving signal. Each decoder (51) is responsive to an address signal for supplying a driving signal from the driver (52) to either one of the switching circuits (80a, 80b) and for applying a ground potential to the other one of the circuits. Accordingly, the sense amplifier block (20) is connected to either one of the memory cell array blocks (10a, 10b ).

Abstract: An input signal is inverted by a CMOS inverter and provided for an output signal line. The CMOS inverter is provided between a power supply and a ground, and its node on the side of the power supply is charged all the time to prevent the potential thereof from being lowered. An output signal provided for the output signal line is delayed by a delay circuit to be applied to a boosting capacitor. The potential of the node is further boosted by this boosting capacitor. Consequently, the potential of the output signal is also boosted. When the potential of the node is raised higher than a supply voltage, an N channel MOSFET for charging is turned off to prevent a reverse flow of a charge.

Abstract: In a dynamic random access memory (DRAM), there is provided a refresh decision circuit which detects the external designation of a self refresh mode, in addition to a CAS before RAS refresh mode, by RAS and CAS signals. By detecting a time period of one cycle of the RAS, the self refresh mode is determined. As a result, the timing of change of the RAS signal is less restricted.

Abstract: In a dynamic random access memory (DRAM), there is provided a refresh decision circuit which detects the external designation of a self refresh mode, in addition to a CAS before RAS refresh mode, by RAS and CAS signals. By detecting a time period of one cycle of the RAS, the self refresh mode is determined. As a result, the timing of change of the RAS signal is less restricted.

Abstract: A dynamic random access memory with self-refresh function, which includes a substrate bias generator (100) adapted to be intermittently driven to apply a bias potential to a semiconductor substrate (15). This memory device comprises a circuit (91) for generating an internal refresh instruction signal (.phi..sub.S) in response to an external refresh instruction signal, a circuit (92, 93) which, in response to the internal refresh instruction signal, generates a refresh enable signal (.phi..sub.R) intermittently at a predetermined interval, a circuit (94, 95, 96, 98) which, in response to the refresh enable signal, refreshes data in the memory cells, and a circuit (99) which, in response to the internal refresh instruction signal and refresh enable signal, activates the substrate bias generator in the same cycle as the cycle of generation of the refresh enable signal and only for a time shorter than the cycle of generation of the refresh enable signal.

Abstract: A MOS dynamic type RAM comprises memory cells (10), dummy cells (11), bit line pairs (BL, BL), word lines (WL), dummy word lines (DWL) and sense amplifiers (12). In a non-active cycle, the potentials of each pair of bit lines (BL, BL) are precharged at 1/2 of a supply potential V.sub.CC. Each sense amplifier (12) operates in an active cycle following the non-active cycle, while each active pull-up circuit (13) pulls up the potential of a higher level one of the pair of bit lines to V.sub.CC. This active cycle is defined by an internal RAS internal signal, which is generated by a NAND circuit (27) in response to an external RAS signal and an RPW signal obtained by delaying the external RAS signal by a delay circuit (20) and having a trailing edge obtained by delaying the trailing edge of the external RAS signal by a prescribed period.