Patents by Inventor Yasuo Imai

Yasuo Imai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8888167
    Abstract: A dash panel has an impact absorption portion formed therein. A suspension tower is connected to the impact absorption portion, so that support stiffness thereof can be ensured. In addition, the suspension tower can be rotated around the front pillar due to an impact, so that an amount of backward movement of the dash panel toward a vehicle interior can be reduced. Thus, a brake booster cannot substantially be moved backward, so that a brake pedal and a steering column can be prevented from being displaced in an upward and backward projecting direction. As a result, a vehicle interior can be protected.
    Type: Grant
    Filed: March 25, 2011
    Date of Patent: November 18, 2014
    Assignee: Toyota Shatai Kabushiki Kaisha
    Inventors: Satoshi Kubo, Yasuo Imai, Yoshinobu Itou, Daisuke Oozawa, Kenji Ishii, Jun Inagaki, Takahiro Tatsuno, Kazuhiko Katou
  • Patent number: 8807886
    Abstract: A hole includes a blade cylinder and at least one first blade portion and at least one second blade portion, which are arranged along the rotation direction at intervals. Each of the first and second blade portions includes an inside blade and an outside blade. In the first and second blade portions that are adjacent to each other along the rotation direction, the sum of the number of cutting edges of the outside blade and the cutting edge of the inside blade of the first blade is three or more, the sum of cutting edges of the outside blade and the cutting edge of the inside blade of the second blade is two or more, the number of the cutting edge of the first blade being different from the number of the cutting edges of the second blade.
    Type: Grant
    Filed: November 17, 2010
    Date of Patent: August 19, 2014
    Assignee: Omi Kogyo Co., Ltd.
    Inventors: Shohei Omi, Yasuo Imai
  • Publication number: 20140225189
    Abstract: In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.
    Type: Application
    Filed: April 23, 2014
    Publication date: August 14, 2014
    Applicants: RENESAS ELECTRONICS CORPORATION, HITACHI ULSI SYSTEMS CO., LTD.
    Inventors: Sumito NUMAZAWA, Yoshito NAKAZAWA, Masayoshi KOBAYASHI, Satoshi KUDO, Yasuo IMAI, Sakae KUBO, Takashi SHIGEMATSU, Akihiro OHNISHI, Kozo UESAWA, Kentaro OISHI
  • Patent number: 8748266
    Abstract: In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.
    Type: Grant
    Filed: November 8, 2011
    Date of Patent: June 10, 2014
    Assignees: Renesas Electronics Corporation, Hitachi Ulsi Systems Co., Ltd.
    Inventors: Sumito Numazawa, Yoshito Nakazawa, Masayoshi Kobayashi, Satoshi Kudo, Yasuo Imai, Sakae Kubo, Takashi Shigematsu, Akihiro Ohnishi, Kozo Uesawa, Kentaro Oishi
  • Publication number: 20130169003
    Abstract: A dash panel has an impact absorption portion formed therein. A suspension tower is connected to the impact absorption portion, so that support stiffness thereof can be ensured. In addition, the suspension tower can be rotated around the front pillar due to an impact, so that an amount of backward movement of the dash panel toward a vehicle interior can be reduced.
    Type: Application
    Filed: March 25, 2011
    Publication date: July 4, 2013
    Applicant: TOYOTA SHATAI KABUSHIKI KAISHA
    Inventors: Satoshi Kubo, Yasuo Imai, Yoshinobu Itou, Daisuke Oozawa, Kenji Ishii, Jun Inagaki, Takahiro Tatsuno, Kazuhiko Katou
  • Patent number: 8354713
    Abstract: In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.
    Type: Grant
    Filed: May 13, 2011
    Date of Patent: January 15, 2013
    Assignees: Renesas Electronics Corporation, Hitachi ULSI Systems Co., Ltd.
    Inventors: Sumito Numazawa, Yoshito Nakazawa, Masayoshi Kobayashi, Satoshi Kudo, Yasuo Imai, Sakae Kubo, Takashi Shigematsu, Akihiro Ohnishi, Kozo Uesawa, Kentaro Oishi
  • Publication number: 20120087755
    Abstract: A plurality of blade tips 4, 5 are provided at the distal end of a blade cylinder having a rotation axis. The blade tips 4, 5 are arranged along a rotation direction at intervals. Each of the blade tips 4, 5 has an outside blade 6 at a farther position from the rotation axis and an inside blade 7 at a closer position to the rotation axis. Each outside blade 6 and the corresponding inside blade 7 are arranged next to each other while being displaced in the rotation direction with the stepped cutting edge 8 in between. In the blade tip 4, which is one of the blade tips 4, 5 adjacent to each other in the rotation direction, the sum of the number of the cutting edge 9 in the outside blade 6 and the number of the cutting edges 11, 12 in the inside blade 7 is three. In the other blade tip 5, the sum of the number of the cutting edge 9 in the outside blade 6 and the number of the cutting edge 10 in the inside blade 7 is two.
    Type: Application
    Filed: November 17, 2010
    Publication date: April 12, 2012
    Applicant: OMI KOGYO CO., LTD.
    Inventors: Shohei Omi, Yasuo Imai
  • Publication number: 20120052675
    Abstract: In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.
    Type: Application
    Filed: November 8, 2011
    Publication date: March 1, 2012
    Applicants: HITACHI ULSI SYSTEMS CO., LTD., RENESAS ELECTRONICS CORPORATION
    Inventors: Sumito Numazawa, Yoshito Nakazawa, Masayoshi Kobayashi, Satoshi Kudo, Yasuo Imai, Sakae Kubo, Takashi Shigematsu, Akihiro Ohnishi, Kozo Uesawa, Kentaro Oishi
  • Patent number: 8076202
    Abstract: In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.
    Type: Grant
    Filed: March 15, 2010
    Date of Patent: December 13, 2011
    Assignees: Renesas Electronics Corporation, Hitachi ULSI Systems Co., Ltd.
    Inventors: Sumito Numazawa, Yoshito Nakazawa, Masayoshi Kobayashi, Satoshi Kudo, Yasuo Imai, Sakae Kubo, Takashi Shigematsu, Akihiro Ohnishi, Kozo Uesawa, Kentaro Oishi
  • Publication number: 20110215398
    Abstract: In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.
    Type: Application
    Filed: May 13, 2011
    Publication date: September 8, 2011
    Applicants: RENESAS ELECTRONICS CORPORATION, HITACHI ULSI SYSTEMS CO., LTD.
    Inventors: Sumito Numazawa, Yoshito Nakazawa, Masayoshi Kobayashi, Satoshi Kudo, Yasuo Imai, Sakae Kubo, Takashi Shigematsu, Akihiro Ohnishi, Kozo Uesawa, Kentaro Oishi
  • Publication number: 20100291242
    Abstract: An ABC transporter protein expression inhibitor comprising, as the active ingredient(s), 0.001 to 100 nM of one or more members selected from among steroid hormones, compounds having a female hormone function, analogous compounds thereof and antagonistic inhibitors therefor; an anticancer composition containing this ABC transporter protein expression inhibitor and an anticancer drug; and cells useful in the development of an anticancer drug. The present invention provides a drug which inhibits the expression of an ABC transporter to thereby overcome resistance to anticancer drugs; cancer cells useful in screening such drugs; and an anticancer drug efficacious even against such a cancer as having acquired resistance to anticancer drugs.
    Type: Application
    Filed: December 28, 2009
    Publication date: November 18, 2010
    Applicants: Yoshikazu SUGIMOTO, Japanese Foundation for Cancer Research, KABUSHIKI KAISHA YAKULT HONSHA
    Inventors: Yoshikazu SUGIMOTO, Satomi Tsukahara, Yasuo Imai
  • Publication number: 20100173461
    Abstract: In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.
    Type: Application
    Filed: March 15, 2010
    Publication date: July 8, 2010
    Applicants: RENESAS TECHNOLOGY CORP., HITACHI ULSI SYSTEMS CO., LTD.
    Inventors: Sumito Numazawa, Yoshito Nakazawa, Masayoshi Kobayashi, Satoshi Kudo, Yasuo Imai, Sakae Kubo, Takashi Shigematsu, Akihiro Ohnishi, Kozo Uesawa, Kentaro Oishi
  • Publication number: 20080249036
    Abstract: An ABC transporter protein expression inhibitor comprising, as the active ingredient(s), 0.001 to 100 nM of one or more members selected from among steroid hormones, compounds having a female hormone function, analogous compounds thereof and antagonistic inhibitors therefor; an anticancer composition containing this ABC transporter protein expression inhibitor and an anticancer drug; and cells useful in the development of an anticancer drug. The present invention provides a drug which inhibits the expression of an ABC transporter to thereby overcome resistance to anticancer drugs; cancer cells useful in screening such drugs; and an anticancer drug efficacious even against such a cancer as having acquired resistance to anticancer drugs.
    Type: Application
    Filed: August 31, 2005
    Publication date: October 9, 2008
    Applicants: Yoshikazu Sugimoto, Japanese Foundation for Cancer Research, KABUSHIKI KAISHA YAKULT HONSHA
    Inventors: Yoshikazu Sugimoto, Satomi Tsukahara, Yasuo Imai
  • Patent number: 7414012
    Abstract: A waterborne lubricant, useful in the plastic working of metals, which imparts a lubricating behavior to the surface of metals in the absence of a conversion coating contains (A) water-soluble inorganic salt and (B) wax, wherein these components are dissolved or dispersed in water and the (B)/(A) solids weight ratio is 0.3 to 1.5. The (C) metal salt of a fatty acid can also be present at a (C)/(A) solids weight ratio of 0.01 to 0.4. The water-soluble inorganic salt (A) can be selected from the sulfates, silicates, borates, molybdates, and tungstates. The wax (B) can be a synthetic wax having a melting point of 70 to 150° C. A lubricating coating is formed by application to give a post-drying add-on of 0.5 to 40 g/m2. A method for using said lubricant is also provided.
    Type: Grant
    Filed: February 7, 2003
    Date of Patent: August 19, 2008
    Assignee: Henkel KGaA
    Inventors: Yasuo Imai, Syuji Nagata, Masayuki Yoshida
  • Publication number: 20070290268
    Abstract: In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.
    Type: Application
    Filed: August 9, 2007
    Publication date: December 20, 2007
    Inventors: Sumito Numazawa, Yoshito Nakazawa, Masayoshi Kobayashi, Satoshi Kudo, Yasuo Imai, Sakae Kubo, Takashi Shigematsu, Akihiro Ohnishi, Kozo Uesawa, Kentaro Oishi
  • Publication number: 20070290239
    Abstract: In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.
    Type: Application
    Filed: July 27, 2007
    Publication date: December 20, 2007
    Inventors: Sumito Numazawa, Yoshito Nakazawa, Masayoshi Kobayashi, Satoshi Kudo, Yasuo Imai, Sakae Kubo, Takashi Shigematsu, Akihiro Ohnishi, Kozo Uesawa, Kentaro Oishi
  • Publication number: 20070278567
    Abstract: In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.
    Type: Application
    Filed: August 3, 2007
    Publication date: December 6, 2007
    Inventors: Sumito Numazawa, Yoshito Nakazawa, Masayoshi Kobayashi, Satoshi Kudo, Yasuo Imai, Sakae Kubo, Takashi Shigematsu, Akihiro Ohnishi, Kozo Uesawa, Kentaro Oishi
  • Publication number: 20070111423
    Abstract: In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.
    Type: Application
    Filed: January 16, 2007
    Publication date: May 17, 2007
    Inventors: Sumito Numazawa, Yoshito Nakazawa, Masayoshi Kobayashi, Satoshi Kudo, Yasuo Imai, Sakee Kubo, Takashi Shigematsu, Akihiro Ohnishi, Kozo Uesawa, Kentaro Oishi
  • Patent number: 7180130
    Abstract: In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.
    Type: Grant
    Filed: September 24, 2004
    Date of Patent: February 20, 2007
    Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.
    Inventors: Sumito Numazawa, Yoshito Nakazawa, Masayoshi Kobayashi, Satoshi Kudo, Yasuo Imai, Sakae Kubo, Takashi Shigematsu, Akihiro Ohnishi, Kozo Uesawa, Kentaro Oishi
  • Publication number: 20050037579
    Abstract: In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.
    Type: Application
    Filed: September 24, 2004
    Publication date: February 17, 2005
    Inventors: Sumito Numazawa, Yoshito Nakazawa, Masayoshi Kobayashi, Satoshi Kudo, Yasuo Imai, Sakae Kubo, Takashi Shigematsu, Akihiro Ohnishi, Kozo Uesawa, Kentaro Oishi