Patents by Inventor Yasuo Imai

Yasuo Imai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6803281
    Abstract: In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.
    Type: Grant
    Filed: February 25, 2004
    Date of Patent: October 12, 2004
    Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.
    Inventors: Sumito Numazawa, Yoshito Nakazawa, Masayoshi Kobayashi, Satoshi Kudo, Yasuo Imai, Sakae Kubo, Takashi Shigematsu, Akihiro Ohnishi, Kozo Uesawa, Kentaro Oishi
  • Publication number: 20040166656
    Abstract: In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.
    Type: Application
    Filed: February 25, 2004
    Publication date: August 26, 2004
    Applicants: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.
    Inventors: Sumito Numazawa, Yoshito Nakazawa, Masayoshi Kobayashi, Satoshi Kudo, Yasuo Imai, Sakae Kubo, Takashi Shigematsu, Akihiro Ohnishi, Kozo Uesawa, Kentaro Oishi
  • Patent number: 6720220
    Abstract: In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.
    Type: Grant
    Filed: December 23, 2002
    Date of Patent: April 13, 2004
    Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.
    Inventors: Sumito Numazawa, Yoshito Nakazawa, Masayoshi Kobayashi, Satoshi Kudo, Yasuo Imai, Sakae Kubo, Takashi Shigematsu, Akihiro Ohnishi, Kozo Uesawa, Kentaro Oishi
  • Publication number: 20030176294
    Abstract: A new aqueous lubricant of one process type used for high efficient cold forging of metallic materials is disclosed. The aqueous lubricant produces less industrial waste than conventional process, requires simple processing steps and provides improved lubricative performance.
    Type: Application
    Filed: May 14, 2003
    Publication date: September 18, 2003
    Inventors: Mamoru Yamamoto, Masayuki Yoshida, Yasuo Imai, Hidehiro Yamaguchi
  • Publication number: 20030167812
    Abstract: An effective and simple controlling process for an aqueous lubricant of one process type used for cold forging of metallic material are explained.
    Type: Application
    Filed: May 14, 2003
    Publication date: September 11, 2003
    Inventors: Mamoru Yamamoto, Masayuki Yoshida, Yasuo Imai, Hidehiro Yamaguchi
  • Publication number: 20030130138
    Abstract: A waterborne lubricant, useful in the plastic working of metals, which imparts a lubricating behavior to the surface of metals in the absence of a conversion coating contains (A) water-soluble inorganic salt and (B) wax, wherein these components are dissolved or dispersed in water and the (B)/(A) solids weight ratio is 0.3 to 1.5. The (C) metal salt of a fatty acid can also be present at a (C)/(A) solids weight ratio of 0.01 to 0.4. The water-soluble inorganic salt (A) can be selected from the sulfates, silicates, borates, molybdates, and tungstates. The wax (B) can be a synthetic wax having a melting point of 70 to 150° C. A lubricating coating is formed by application to give a post-drying add-on of 0.5 to 40 g/m2. A method for using said lubricant is also provided.
    Type: Application
    Filed: February 7, 2003
    Publication date: July 10, 2003
    Inventors: Yasuo Imai, Syuji Nagata, Masayuki Yoshida
  • Publication number: 20030130137
    Abstract: A waterborne lubricant, useful in the plastic working of metals, which imparts a lubricating behavior to the surface of metals in the absence of a conversion coating contains (A) water-soluble inorganic salt, (B) lubricating agent selected from molybdenum disulfide and graphite, and (C) wax wherein these components are dissolved or dispersed in water, the (B)/(A) solids weight ratio is 1.0 to 5.0, and the (C)/(A) solids weight ratio is 0.1 to 1.0. The water-soluble inorganic salt (A) can be selected from the sulfates, silicates, borates, molybdates, and tungstates. The wax (C) can be a water-dispersed natural or synthetic wax having a melting point of 70 to 150° C. A lubricating coating is formed by application to give a post-drying add-on of 0.5 to 40 g/m2. A method for using said lubricant is also provided.
    Type: Application
    Filed: February 7, 2003
    Publication date: July 10, 2003
    Inventors: Yasuo Imai, Syuji Nagata, Masayuki Yoshida
  • Publication number: 20030124806
    Abstract: In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.
    Type: Application
    Filed: December 23, 2002
    Publication date: July 3, 2003
    Applicant: Hitachi, Ltd.
    Inventors: Sumito Numazawa, Yoshito Nakazawa, Masayoshi Kobayashi, Satoshi Kudo, Yasuo Imai, Sakae Kubo, Takashi Shigematsu, Akihiro Ohnishi, Kozo Uesawa, Kentaro Oishi
  • Patent number: 6512265
    Abstract: In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.
    Type: Grant
    Filed: March 27, 2002
    Date of Patent: January 28, 2003
    Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Sumito Numazawa, Yoshito Nakazawa, Masayoshi Kobayashi, Satoshi Kudo, Yasuo Imai, Sakae Kubo, Takashi Shigematsu, Akihiro Ohnishi, Kozo Uesawa, Kentaro Oishi
  • Patent number: 6455476
    Abstract: A lubricant composition for the plastic working of metals that does not require a phosphate undercoating, is waterborne, requires only a simple application process of immersion or spraying followed by drying, and provides an excellent lubricating performance comprises synthetic resin, water-soluble inorganic salt, and water. The weight ratio of the content of salt to that of synthetic resin is from 0.25:1 to 9: 1. This composition can also contain liquid and/or solid lubricating agent(s) and an extreme pressure additive.
    Type: Grant
    Filed: December 7, 2000
    Date of Patent: September 24, 2002
    Assignee: Henkel Corporation
    Inventors: Yasuo Imai, Shuji Nagata
  • Publication number: 20020098656
    Abstract: In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.
    Type: Application
    Filed: March 27, 2002
    Publication date: July 25, 2002
    Applicant: Hitachi, Ltd.
    Inventors: Sumito Numazawa, Yoshito Nakazawa, Masayoshi Kobayashi, Satoshi Kudo, Yasuo Imai, Sakae Kubo, Takashi Shigematsu, Akihiro Ohnishi, Kozo Uesawa, Kentaro Oishi
  • Patent number: 6410959
    Abstract: In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.
    Type: Grant
    Filed: September 21, 2001
    Date of Patent: June 25, 2002
    Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Sumito Numazawa, Yoshito Nakazawa, Masayoshi Kobayashi, Satoshi Kudo, Yasuo Imai, Sakae Kubo, Takashi Shigematsu, Akihiro Ohnishi, Kozo Uesawa, Kentaro Oishi
  • Publication number: 20020009867
    Abstract: In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.
    Type: Application
    Filed: September 21, 2001
    Publication date: January 24, 2002
    Applicant: Hitachi, Ltd.
    Inventors: Sumito Numazawa, Yoshito Nakazawa, Masayoshi Kobayashi, Satoshi Kudo, Yasuo Imai, Sakae Kubo, Takashi Shigematsu, Akihiro Ohnishi, Kozo Uesawa, Kentaro Oishi
  • Patent number: 6330871
    Abstract: The present invention provides a cylinder head-integrated cylinder block in which assembly is easy and a thickness of an aluminum member is not increased even if an integral cylinder head is molded by using the aluminum member and which is lightweight and has strength at a high temperature and a process for manufacturing the cylinder head-integrated cylinder block.
    Type: Grant
    Filed: April 18, 2000
    Date of Patent: December 18, 2001
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Yasunobu Jufuku, Makoto Ueno, Akihiko Hirooka, Yasuo Imai, Tatsumi Furukubo
  • Patent number: 6307231
    Abstract: In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.
    Type: Grant
    Filed: July 21, 2000
    Date of Patent: October 23, 2001
    Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Sumito Numazawa, Yoshito Nakazawa, Masayoshi Kobayashi, Satoshi Kudo, Yasuo Imai, Sakae Kubo, Takashi Shigematsu, Akihiro Ohnishi, Kozo Uesawa, Kentaro Oishi
  • Patent number: 6168996
    Abstract: In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.
    Type: Grant
    Filed: August 20, 1998
    Date of Patent: January 2, 2001
    Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Sumito Numazawa, Yoshito Nakazawa, Masayoshi Kobayashi, Satoshi Kudo, Yasuo Imai, Sakae Kubo, Takashi Shigematsu, Akihiro Ohnishi, Kozo Uesawa, Kentaro Oishi
  • Patent number: 6094550
    Abstract: An electrophotography developing apparatus has been developed which can protect a developer holder and a layer thickness control member from damage. The device also prevents internal scattering of the developer while preventing a surplus supply of the developer to both ends on the peripheral surface of the developer holder. The unique advantages of the invention are derived through the utilization of sealing members having different elastic properties, which assume both bulk removal of excess developer while providing the needed uniform developer thickness. Another embodiment of the invention has the width of the layer thickness control member in a longitudinal direction set wider than the width of the developer holder in a longitudinal direction, and both side edges of the layer thickness control member are positioned outside both side edges of the developer holder.
    Type: Grant
    Filed: May 27, 1998
    Date of Patent: July 25, 2000
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Eiichi Kido, Shigeyuki Wakada, Toshihide Ohgoshi, Yoshinori Ohtsuka, Hiroshige Araki, Yasuo Imai, Hiroshi Ishii, Yuhi Yui
  • Patent number: 5988956
    Abstract: A hole cutter having a body provided with first and second types of cutting teeth. The cutter facilitates the discharge of cutting chips during machining of a workpiece. The tooth depth of the left and right sections of each of the second type of teeth is smaller than that of the left and right sections of each of the first type of teeth. The tooth depth of the middle section of each tooth of the second type is greater than that of the middle section of each tooth of the first type. A linear flattening section is provided at the middle portion of a second blade edge of each tooth of the second type. The flattening section causes each cutting chip to be shaped in a strip-like manner when removed from the workpiece. This separates the ends of the cutting chips from each other and prevents the chips from becoming entangled to one another.
    Type: Grant
    Filed: November 6, 1996
    Date of Patent: November 23, 1999
    Assignee: Omi Kogyo Co., Ltd.
    Inventors: Shohei Omi, Yasuo Imai
  • Patent number: 5640651
    Abstract: A developer cartridge for image forming apparatuses which performs development to form images with non-magnetic, one-component type developer. The cartridge includes a developing roller for supplying developer to a photoconductor drum, a developer feed roller in non-contact with the developing roller for supply developer to the developing roller, and a developer-layer thickness control member for controlling the thickness of the developer layer on the developing roller. The developer feed roller is shaped as a regular polygonal prism. Since no recesses are formed in the surface of the regular polygonal prism, driving torque does not increase when developer is scrubbed from the prism, thus ensuring consistent operation and improved image quality. Non-magnetic, one-component type developer is compressed onto the developing roller by supplying the developer via the developer feed roller into a bottleneck between the developing roller and a developer applying member.
    Type: Grant
    Filed: November 29, 1995
    Date of Patent: June 17, 1997
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Keiji Katoh, Hiroshige Araki, Yasuo Imai, Shigeyuki Wakada, Eiichi Kido, Toshihiro Ota, Yuhi Yui
  • Patent number: D394450
    Type: Grant
    Filed: August 15, 1995
    Date of Patent: May 19, 1998
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Keiji Katoh, Hiroshige Araki, Yasuo Imai