Abstract: An evaluation method of a silicon epitaxial wafer, including using a photoluminescence (PL) measuring apparatus to measure a PL spectrum of the mirror wafer and adjusting the apparatus so emission intensity of a TO-line becomes 30000 to 50000 counts, irradiating the silicon epitaxial wafer with an electron beam, measuring PL spectrum from an electron beam irradiation region, and sorting out and accepting a silicon epitaxial wafer which has emission intensity resulting from a CiCs defect of the PL spectrum being 0.83% or less of the emission intensity of the TO-line and from a CiOi defect being 6.5% or less of the emission intensity of the TO-line.

Abstract: A method for evaluating a carbon concentration where ions of a predetermined element are implanted into a silicon wafer, and then a carbon concentration is measured by a low-temperature PL method from an emission intensity of a CiCs composite, where the ions are implanted under implantation conditions of 1.1×1011×[atomic weight of the implanted element]?0.73<implantation amount (cm?2)<4.3×1011×[atomic weight of the implanted element]?0.73, and the carbon concentration is evaluated. A method for evaluating a carbon concentration makes it possible to measure with high sensitivity, a carbon concentration in a surface layer of 1 to 2 ?m, which is a photodiode region in an image sensor.

Abstract: A method for evaluating a carbon concentration where ions of a predetermined element are implanted into a silicon wafer, and then a carbon concentration is measured by a low-temperature PL method from an emission intensity of a CiCs composite, where the ions are implanted under implantation conditions of 1.1×1011×[atomic weight of the implanted element]?0.73<implantation amount (cm?2)<4.3×1011×[atomic weight of the implanted element]?0.73, and the carbon concentration is evaluated. A method for evaluating a carbon concentration makes it possible to measure with high sensitivity, a carbon concentration in a surface layer of 1 to 2 ?m which is a photodiode region in an image sensor.

Abstract: A method for manufacturing a silicon epitaxial wafer includes: preparing a test silicon wafer in advance, forming the multilayer film on a surface of the test silicon wafer, and measuring a warp direction and a warp amount (Warp) W of the silicon wafer having the multilayer film formed thereon; and selecting a silicon wafer as a device formation substrate and conditions for forming an epitaxial layer which is formed on the silicon wafer as the device formation substrate in such a manner that a warp which cancels out the measured warp amount W is formed in a direction opposite to the measured warp direction, and forming the epitaxial layer on a surface of the selected silicon wafer as the device formation substrate where the multilayer film is formed under the selected conditions for forming the epitaxial layer.

Abstract: An evaluation method of a silicon epitaxial wafer, including using a photoluminescence (PL) measuring apparatus to measure a PL spectrum of the mirror wafer and adjusting the apparatus so emission intensity of a TO-line becomes 30000 to 50000 counts, irradiating the silicon epitaxial wafer with an electron beam, measuring PL spectrum from an electron beam irradiation region, and sorting out and accepting a silicon epitaxial wafer which has emission intensity resulting from a CiCs defect of the PL spectrum being 0.83% or less of the emission intensity of the TO-line and from a CiOi defect being 6.5% or less of the emission intensity of the TO-line.

Abstract: A manufacturing method of a silicon epitaxial wafer having an epitaxial layer grown on a mirror wafer of silicon, including: using a PL measuring apparatus to measure photoluminescence (PL) spectrum of the mirror wafer and adjusting the apparatus so emission intensity of a TO-line becomes 30000 to 50000 counts, irradiating the silicon epitaxial wafer with an electron beam, measuring PL spectrum from an electron beam irradiation region, and sorting out and accepting a silicon epitaxial wafer which has emission intensity resulting from a CiCs defect of the PL spectrum being 0.83% or less of the emission intensity of the TO-line and from a CiOi defect being 6.5% or less of the emission intensity of the TO-line. The method enables sorting out a silicon epitaxial wafer which realizes a negligible level of white flaw failures in case of manufacturing an imaging element with the use of the silicon epitaxial wafer.

Abstract: A method for manufacturing a silicon epitaxial wafer includes: preparing a test silicon wafer in advance, forming the multilayer film on a surface of the test silicon wafer, and measuring a warp direction and a warp amount (Warp) W of the silicon wafer having the multilayer film formed thereon; and selecting a silicon wafer as a device formation substrate and conditions for forming an epitaxial layer which is formed on the silicon wafer as the device formation substrate in such a manner that a warp which cancels out the measured warp amount W is formed in a direction opposite to the measured warp direction, and forming the epitaxial layer on a surface of the selected silicon wafer as the device formation substrate where the multilayer film is formed under the selected conditions for forming the epitaxial layer.

Abstract: A manufacturing method of a silicon epitaxial wafer having an epitaxial layer grown on a mirror wafer of silicon, including: using a PL measuring apparatus to measure photoluminescence (PL) spectrum of the mirror wafer and adjusting the apparatus so emission intensity of a TO-line becomes 30000 to 50000 counts, irradiating the silicon epitaxial wafer with an electron beam, measuring PL spectrum from an electron beam irradiation region, and sorting out and accepting a silicon epitaxial wafer which has emission intensity resulting from a CiCs defect of the PL spectrum being 0.83% or less of the emission intensity of the TO-line and from a CiOi defect being 6.5% or less of the emission intensity of the TO-line. The method enables sorting out a silicon epitaxial wafer which realizes a negligible level of white flaw failures in case of manufacturing an imaging element with the use of the silicon epitaxial wafer.

Abstract: The method of forming a thin film feeds a raw material gas causing a reversible decomposition reaction toward an upper surface of substrate placed on a placing table in a processing container; decomposes the raw material gas with a predetermined decomposing scheme thereby forming a thin film of the raw material gas on the surface of the substrate; and feeds a decomposition restraint gas having a characteristic of restraining a thermal decomposition of the raw material gas separately from the raw material gas toward a peripheral portion of the substrate when the raw material gas is fed to the substrate, thereby restraining the thermal decomposition of the raw material gas and selectively preventing the thin film from being formed in the peripheral portion of the substrate.

Abstract: A trap mechanism for trapping exhaust gas from a process chamber. The trap assembly includes a housing containing a plurality of trap units. The plurality of trap units are arranged successively along a flow direction of said exhaust gas. Each trap unit includes a set of trap panels parallel to each other and spaced apart from each other. The two opposite surfaces with a larger area of each trap panel are oriented substantially parallel to a flow direction of the exhaust gas flow. The two opposite surfaces with a smaller area of each trap panels are oriented orthogonal to the exhaust gas flow.

Abstract: When a recess is formed in a SiCOH film, C is removed from the film to form a damage layer. If the damage layer is removed by hydrofluoric acid or the like, the surface becomes hydrophobic. By supplying a boron compound gas, a silicon compound gas or a gas containing trimethyl aluminum to the SiCOH film, B, Si or Al is adsorbed on the SiCOH film. These atoms bond with Ru and a Ru film is easily formed on the SiCOH film. The Ru film is formed using, for example, Ru3(CO)12 gas and CO gas. Copper is filled in the recess and an upper side wiring structure is formed by carrying out CMP processing.

Abstract: A Cu wiring forming method forms Cu wiring in a recess of a predetermined pattern including a trench formed in an insulating film on a substrate surface. The method includes: forming a barrier film at least on a surface of the recess; forming a Cu film by PVD to fill the recess with the Cu film; forming an additional layer on the Cu film; polishing an entire surface by CMP to form the Cu wiring in the recess; forming a metal cap including a manganese oxide film on an entire surface including the insulating film and the Cu wiring of the substrate after performing the CMP polishing; and forming a dielectric cap on the metal cap.

Abstract: Disclosed is a method for film formation, comprising allowing a treatment gas stream containing a metal carbonyl-containing treatment gas and a carbon monoxide-containing carrier gas to flow into a region on the upper outside of the outer periphery of a substrate to be treated in a diameter direction of the substrate while avoiding the surface of the substrate and diffusing the metal carbonyl from the treatment gas stream into the surface of the substrate to form a metal film on the surface of the substrate.

Abstract: A trap mechanism for trapping exhaust gas from a process chamber. The trap assembly includes a housing containing a plurality of trap units. The plurality of trap units are arranged successively along a flow direction of said exhaust gas. Each trap unit includes a set of trap panels parallel to each other and spaced apart from each other. The two opposite surfaces with a larger area of each trap panel are oriented substantially parallel to a flow direction of the exhaust gas flow. The two opposite surfaces with a smaller area of each trap panels are oriented orthogonal to the exhaust gas flow.

Abstract: A semiconductor device manufacturing method includes: modifying a surface of a burying recess, of which surface is hydrophobic and which is formed in a dielectric film, to a hydrophilic state by supplying a plasma containing H ions and H radicals or a plasma containing NHx (x being 1, 2 or 3) ions and NHx radicals to the dielectric film formed on a substrate and containing silicon, carbon, hydrogen and oxygen, a bottom portion of the burying recess being exposed with a lower conductive layer; and directly forming an adhesion film formed of a Ru film on the hydrophilic surface of the recess. The method further includes burying copper forming a conductive path in the recess.

Abstract: Provided is a mounting table structure for use in forming a thin film on a surface of a target object mounted on the mounting table structure by using a raw material gas including an organic metal compound in a processing chamber. The mounting table structure includes: a mounting table main body which mounts thereon the target object and has therein a heater; and a base which supports the mounting table main body while surrounding a side surface and a bottom surface of the mounting table main body, the base having therein a coolant path where a coolant flows therethrough and being maintained at a temperature higher than the solidification temperature or the liquefaction temperature of the raw material gas, but lower than the decomposition temperature of the raw material gas.

Abstract: A method for calculating a warpage of a bonded SOI wafer includes: assuming that the epitaxial growth SOI wafer is a silicon single crystal wafer having the same dopant concentration as dopant concentration of the bond wafer; calculating a warpage A that occurs at the time of performing the epitaxial growth relative to the assumed silicon single crystal wafer; calculating a warpage B caused due to a thickness of the BOX layer of the epitaxial growth SOI wafer; determining a measured value of a warpage of the base wafer before bonding as a warpage C; and calculating a sum of the warpages (A+B+C) as the warpage of the bonded SOI wafer.

Abstract: Provided is a placing table structure which is disposed in a processing container and has a subject to be processed thereon so as to form a thin film on the subject in the processing container by using raw material gas which generates thermal decomposition reaction having reversibility. The placing table structure is provided with a placing table for the purpose of placing the subject to be processed on a placing surface, i.e., an upper surface of the placing table structure, and a decomposition suppressing gas supply means which is arranged in the placing table for the purpose of supplying decomposition suppressing gas, which suppresses thermal decomposition of the raw material gas, toward a peripheral section of the subject placed on the placing surface of the placing table.

Abstract: When a recess is formed in a SiCOH film, C is removed from the film to form a damage layer. If the damage layer is removed by hydrofluoric acid or the like, the surface becomes hydrophobic. By supplying a boron compound gas, a silicon compound gas or a gas containing trimethyl aluminum to the SiCOH film, B, Si or Al is adsorbed on the SiCOH film. These atoms bond with Ru and a Ru film is easily formed on the SiCOH film. The Ru film is formed using, for example, Ru3(CO)12 gas and CO gas. Copper is filled in the recess and an upper side wiring structure is formed by carrying out CMP processing.

Abstract: There is provided a sputter device in which a conductive target having a planar and circular shape is disposed so as to face a workpiece substrate mounted on a mounting part located within a vacuum chamber, includes: a direct current power supply configured to apply a negative direct current voltage to the target; an opposing electrode installed at the opposite side of the workpiece substrate from the target so as to face the target; and a target high-frequency power supply connected to the target and configured to supply high-frequency power to the target in order to generate a high-frequency electric field between the opposing electrode and the target, wherein the distance between the target and the workpiece substrate during a sputtering process being 30 mm or less.