Patents by Inventor Yasushi Mizusawa
Yasushi Mizusawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8859422Abstract: A method of forming a Cu wiring in a trench or hole formed in a substrate is provided. The method includes forming a barrier film on the surface of the trench or hole, forming a Ru film on the barrier film, and embedding Cu in the trench or hole by forming a Cu film on the Ru film using PVD while annealing the substrate such that migration of copper into the trench or hole occurs.Type: GrantFiled: January 26, 2012Date of Patent: October 14, 2014Assignee: Tokyo Electron LimitedInventors: Tadahiro Ishizaka, Atsushi Gomi, Takara Kato, Osamu Yokoyama, Takashi Sakuma, Chiaki Yasumuro, Hiroyuki Toshima, Tatsuo Hatano, Yasushi Mizusawa, Masamichi Hara, Kenzi Suzuki
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Publication number: 20140287163Abstract: A method of forming a Cu wiring in a trench or hole formed in a substrate is provided. The method includes forming a barrier film on the surface of the trench or hole, forming a Ru film on the barrier film, and embedding Cu in the trench or hole by forming a Cu film on the Ru film using PVD while annealing the substrate such that migration of copper into the trench or hole occurs.Type: ApplicationFiled: June 6, 2014Publication date: September 25, 2014Inventors: Tadahiro ISHIZAKA, Atsushi GOMI, Takara FUKUSHIMA, Osamu YOKOYAMA, Takashi SAKUMA, Chiaki YASUMURO, Hiroyuki TOSHIMA, Tatsuo HATANO, Yasushi MIZUSAWA, Masamichi HARA, Kenzi SUZUKI
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Publication number: 20140186977Abstract: A method for calculating a warpage of a bonded SOI wafer includes: assuming that the epitaxial growth SOI wafer is a silicon single crystal wafer having the same dopant concentration as dopant concentration of the bond wafer; calculating a warpage A that occurs at the time of performing the epitaxial growth relative to the assumed silicon single crystal wafer; calculating a warpage B caused due to a thickness of the BOX layer of the epitaxial growth SOI wafer; determining a measured value of a warpage of the base wafer before bonding as a warpage C; and calculating a sum of the warpages (A+B+C) as the warpage of the bonded SOI wafer.Type: ApplicationFiled: August 21, 2012Publication date: July 3, 2014Applicant: SHIN-ETSU HANDOTAI CO., LTD.Inventors: Isao Yokokawa, Hiroji Aga, Yasushi Mizusawa
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Publication number: 20140045329Abstract: A Cu wiring forming method forms Cu wiring in a recess of a predetermined pattern including a trench formed in an insulating film on a substrate surface. The method includes: forming a barrier film at least on a surface of the recess; forming a Cu film by PVD to fill the recess with the Cu film; forming an additional layer on the Cu film; polishing an entire surface by CMP to form the Cu wiring in the recess; forming a metal cap including a manganese oxide film on an entire surface including the insulating film and the Cu wiring of the substrate after performing the CMP polishing; and forming a dielectric cap on the metal cap.Type: ApplicationFiled: August 8, 2013Publication date: February 13, 2014Applicant: TOKYO ELECTRON LIMITEDInventors: Tadahiro ISHIZAKA, Atsushi Gomi, Kenji Suzuki, Tatsuo Hatano, Hiroyuki Toshima, Yasushi Mizusawa
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Publication number: 20140030886Abstract: A copper (Cu) wiring forming method includes forming a barrier film on the entire surface of a wafer which has a trench, forming a ruthenium (Ru) film on the barrier film, and filling the trench by forming a pure copper film on the ruthenium film by a physical vapor deposition (PVD). The method further includes forming a copper alloy film on the pure copper film by the PVD, forming a copper wiring by polishing the entire surface by a chemical mechanical polishing, forming a cap layer made of a dielectric material on the copper wiring, and segregating an alloy component included in the copper alloy film in a region including a portion corresponding an interface between the copper wiring and the cap layer.Type: ApplicationFiled: September 30, 2013Publication date: January 30, 2014Applicant: TOKYO ELECTRON LIMITEDInventors: Takara FUKUSHIMA, Tadahiro Ishizaka, Atsushi Gomi, Tatsuo Hatano, Yasushi Mizusawa
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Publication number: 20130237053Abstract: A film forming method which generates metal ions from a metal target with a plasma in a processing chamber and attracts the metal ions with a bias to deposit a metal thin film on a target object wherein trenches are formed. The method includes: generating metal ions from a target and attracting the metal ions into a target object with a bias to form a base film in a trench; ionizing a rare gas with the bias in a state where no metal ion is generated and attracting the generated ions into the target object to etch the base film; and plasma sputtering the target to generate metal ions and attracting the metal ions into the object with a high frequency power for bias to deposit a main film as a metal film, while reflowing the main film by heating.Type: ApplicationFiled: September 26, 2011Publication date: September 12, 2013Applicant: Tokyo Electron LimitedInventors: Tadahiro Ishizaka, Takashi Sakuma, Tatsuo Hatano, Osamu Yokoyama, Atsushi Gomi, Chiaki Yasumuro, Toshihiko Fukushima, Hiroyuki Toshima, Masaya Kawamata, Yasushi Mizusawa, Takara Kato
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Publication number: 20130203250Abstract: A semiconductor device manufacturing method includes: modifying a surface of a burying recess, of which surface is hydrophobic and which is formed in a dielectric film, to a hydrophilic state by supplying a plasma containing H ions and H radicals or a plasma containing NHx (x being 1, 2 or 3) ions and NHx radicals to the dielectric film formed on a substrate and containing silicon, carbon, hydrogen and oxygen, a bottom portion of the burying recess being exposed with a lower conductive layer; and directly forming an adhesion film formed of a Ru film on the hydrophilic surface of the recess. The method further includes burying copper forming a conductive path in the recess.Type: ApplicationFiled: August 3, 2012Publication date: August 8, 2013Applicant: Tokyo Electron LimitedInventors: Tadahiro Ishizaka, Atsushi Gomi, Kenzi Suzuki, Tatsuo Hatano, Yasushi Mizusawa
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Patent number: 8440563Abstract: Provided is a film-forming method for performing a film-forming process on a surface of a target substrate to be processed in an evacuable processing chamber, a recessed portion being formed on the surface of the target substrate. The method includes a transition metal-containing film processing process in which a transition metal-containing film is formed by a heat treatment by using a source gas containing a transition metal; and a metal film forming process in which a metal film containing an element of the group VIII of the periodic table is formed.Type: GrantFiled: January 10, 2011Date of Patent: May 14, 2013Assignee: Tokyo Electron LimitedInventors: Kenji Matsumoto, Yasushi Mizusawa
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Publication number: 20130081938Abstract: A magnetron sputtering apparatus in which a target is disposed to face a substrate includes a magnet array body including a magnet group arranged on a base body, and a rotating mechanism for rotating the magnet array body around an axis perpendicular to the substrate. In the magnet array body, N poles and S poles constituting the magnet group are arranged to be spaced from each other along a surface facing the target such that a plasma is generated based on a drift of electrons by a cusp magnetic field. Magnets located on the outermost periphery of the magnet group are arranged in a line to prevent the electrons from being released from constraint of the cusp magnetic field and jumping out of the cusp magnetic field. A distance between the target and the substrate during sputtering is equal to or less than 30 mm.Type: ApplicationFiled: September 28, 2012Publication date: April 4, 2013Inventors: Shigeru MIZUNO, Hiroyuki TOSHIMA, Atsushi GOMI, Tetsuya MIYASHITA, Tatsuo HATANO, Yasushi MIZUSAWA
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Patent number: 8408025Abstract: A raw material recovery method for recovering a raw material of an organic metallic compound, which has the property of being stable toward a specific refrigerant without being decomposed thereby, from exhaust gas discharged from a treatment container in which a metallic thin film is formed on the surface of an object to be treated by using source gas obtained by vaporizing the raw material is characterized by being provided with a solidification step for solidifying the unreacted source gas by cooling the exhaust gas by bringing the exhaust gas into contact with the refrigerant and reprecipitating the raw material, and a recovery step for separating and recovering the raw material reprecipitated in the solidification step from the refrigerant. To provide a method for controlling an exhaust gas flow rate so that flow of gas in a processing chamber becomes uniform.Type: GrantFiled: August 4, 2009Date of Patent: April 2, 2013Assignee: Tokyo Electron LimitedInventors: Atsushi Gomi, Yasushi Mizusawa, Tatsuo Hatano, Masamichi Hara, Kaoru Yamamoto, Chiaki Yasumuro
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Patent number: 8399353Abstract: A method of forming a Cu wiring in a trench or hole formed in a substrate is provided. The method includes forming a barrier film on the surface of the trench or hole, forming a Ru film on the barrier film, and embedding copper in the trench or hole by forming a Cu film on the Ru film using PVD while heating the substrate such that migration of copper into the trench or hole occurs.Type: GrantFiled: April 6, 2011Date of Patent: March 19, 2013Assignee: Tokyo Electron LimitedInventors: Tadahiro Ishizaka, Atsushi Gomi, Takara Kato, Osamu Yokoyama, Takashi Sakuma, Chiaki Yasumuro, Hiroyuki Toshima, Tatsuo Hatano, Yasushi Mizusawa, Masamichi Hara
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Patent number: 8372739Abstract: An interconnect structure for an integrated circuit and method of forming the interconnect structure. The method includes depositing a metallic layer containing a reactive metal in an interconnect opening formed within a dielectric material containing a dielectric reactant element, thermally reacting at least a portion of the metallic layer with at least a portion of the dielectric material to form a diffusion barrier primarily containing a compound of the reactive metal from the metallic layer and the dielectric reactant element from the dielectric material, and filling the interconnect opening with Cu metal, where the diffusion barrier surrounds the Cu metal within the opening. The reactive metal can be Co, Ru, Mo, W, or Ir, or a combination thereof. The interconnect opening can be a trench, a via, or a dual damascene opening.Type: GrantFiled: March 26, 2007Date of Patent: February 12, 2013Assignee: Tokyo Electron LimitedInventors: Tadahiro Ishizaka, Satohiko Hoshino, Kuzuhiro Hamamoto, Shigeru Mizuno, Yasushi Mizusawa
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Publication number: 20120315404Abstract: A method for vapor deposition on a substrate in a vapor deposition system having a process space separated from a transfer space. The method disposes a substrate in a process space of a processing system that is vacuum isolated from a transfer space of the processing system, processes the substrate at either of a first position or a second position in the process space while maintaining vacuum isolation from the transfer space by way of a movement accommodating sealing material, and deposits a material on the substrate at either the first position or the second position.Type: ApplicationFiled: August 1, 2012Publication date: December 13, 2012Applicant: TOKYO ELECTRON LIMITEDInventors: Yicheng LI, Tadahiro ISHIZAKA, Kaoru YAMAMOTO, Atsushi GOMI, Masamichi HARA, Toshiaki FUJISATO, Jacques FAGUET, Yasushi MIZUSAWA
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Patent number: 8277889Abstract: A film formation method is disclosed for depositing a metal film on a target substrate by supplying a metal carbonyl source in gas phase to a surface of the target substrate and decomposing the source near the surface of the target substrate. The method includes a step of preferentially decomposing the metal carbonyl source in an area near the outer peripheral portion of the target substrate when the metal film is being deposited on the surface of the target substrate. As a result, a CO concentration in the atmosphere is increased locally near the outer peripheral portion of the target substrate and the depositing of the metal film on the outer peripheral portion is better controlled.Type: GrantFiled: February 19, 2008Date of Patent: October 2, 2012Assignee: Tokyo Electron LimitedInventors: Atsushi Gomi, Yasushi Mizusawa, Tatsuo Hatano, Masamichi Hara, Osamu Yokoyama, Satoshi Taga
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Patent number: 8273409Abstract: Disclosed is a method for film formation, characterized by comprising allowing a treatment gas stream containing a metal carbonyl-containing treatment gas and a carbon monoxide-containing carrier gas to flow into a region on the upper outside of the outer periphery of a substrate to be treated in a diameter direction of the substrate while avoiding the surface of the substrate and diffusing the metal carbonyl from the treatment gas stream into the surface of the substrate to form a metal film on the surface of the substrate.Type: GrantFiled: June 10, 2011Date of Patent: September 25, 2012Assignee: Tokyo Electron LimitedInventors: Masamichi Hara, Yasushi Mizusawa, Satoshi Taga, Atsushi Gomi, Tatsuo Hatano
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Patent number: 8268078Abstract: A method and system is described for reducing particle contamination of a substrate in a deposition system. The deposition system comprises one or more particle diffusers disposed therein and configured to prevent or partially prevent the passage of film precursor particles, or break-up or partially break-up film precursor particles. The particle diffuser may be installed in the film precursor evaporation system, or the vapor delivery system, or the vapor distribution system, or two or more thereof.Type: GrantFiled: March 16, 2006Date of Patent: September 18, 2012Assignee: Tokyo Electron LimitedInventors: Kenji Suzuki, Atsushi Gomi, Masamichi Hara, Yasushi Mizusawa
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Publication number: 20120222782Abstract: In a Cu wiring forming method which is followed by a post-process including a treatment of a temperature of 500° C. or higher, an adhesion film made of a metal having a lattice spacing that differs from the lattice spacing of Cu by 10% or less is formed on a substrate having a trench and/or a hole in the surface such that the adhesion film is deposited on at least the bottom and side surfaces of the trench and/or hole. A Cu film is formed on the adhesion film to fill the trench and/or hole. An annealing process is performed on the substrate on which the Cu film has been formed at 350° C. or higher. The CU film is polished to leave only the part of the Cu film which corresponds to the trench and/or hole. A cap is formed on the polished Cu film to form a Cu wiring.Type: ApplicationFiled: August 27, 2010Publication date: September 6, 2012Applicant: TOKYO ELECTRON LIMITEDInventors: Atsushi Gomi, Yasushi Mizusawa, Tatsuo Hatano, Osamu Yokoyama, Tadahiro Ishizaka, Chiaki Yasumuro, Takara Kato
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Publication number: 20120196437Abstract: A method of forming a Cu wiring in a trench or hole formed in a substrate is provided. The method includes forming a barrier film on the surface of the trench or hole, forming a Ru film on the barrier film, and embedding copper in the trench or hole by forming a Cu film on the Ru film using PVD while heating the substrate such that migration of copper into the trench or hole occurs.Type: ApplicationFiled: April 6, 2011Publication date: August 2, 2012Applicant: TOKYO ELECTRON LIMITEDInventors: Tadahiro ISHIZAKA, Atsushi GOMI, Takara KATO, Osamu YOKOYAMA, Takashi SAKUMA, Chiaki YASUMURO, Hiroyuki TOSHIMA, Tatsuo HATANO, Yasushi MIZUSAWA, Masamichi HARA
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Publication number: 20120196052Abstract: A method of forming a Cu wiring in a trench or hole formed in a substrate is provided. The method includes forming a barrier film on the surface of the trench or hole, forming a Ru film on the barrier film, and embedding Cu in the trench or hole by forming a Cu film on the Ru film using PVD while annealing the substrate such that migration of copper into the trench or hole occurs.Type: ApplicationFiled: January 26, 2012Publication date: August 2, 2012Applicant: TOKYO ELECTRON LIMITEDInventors: Tadahiro ISHIZAKA, Atsushi GOMI, Takara KATO, Osamu YOKOYAMA, Takashi SAKUMA, Chiaki YASUMURO, Hiroyuki TOSHIMA, Tatsuo HATANO, Yasushi MIZUSAWA, Masamichi HARA, Kenzi SUZUKI
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Publication number: 20120064717Abstract: In a CVD-Ru film forming method, an Ru-film is formed on a substrate by means of CVD using a ruthenium carbonyl as a film-forming material before forming a Cu film. Then the substrate on which the aforementioned Ru film is formed is annealed in a hydrogen containing atmosphere.Type: ApplicationFiled: September 12, 2011Publication date: March 15, 2012Applicant: TOKYO ELECTRON LIMITEDInventors: Takara KATO, Yasushi Mizusawa, Tatsuo Hatano, Atsushi Gomi, Chiaki Yasumuro, Osamu Yokoyama