Abstract: A snapback device functions as a semiconductor protection circuit to prevent damage to integrated circuits due to events such as electrostatic discharge and the like. The snapback device is capable of carrying considerable current at a reduced voltage once it snaps back into bipolar operation mode after its trigger point is achieved. The snapback device includes the advantage of a low breakdown voltage which enables the snapback device to snap back into bipolar mode before damage is done to active circuit components due to their breakdown voltages being exceeded. The snapback device includes n+ active areas formed within a p-well substrate region and each active area includes a polysilicon film overlapping the active area but insulated therefrom by a dielectric film. Each n+ active area and polysilicon film are coupled by a conductive film and the components combine to form one electric node.

Abstract: The present invention provides a method of forming a trench capacitor in an input/output region and a trench isolation structure in an active device region and a method of manufacturing an integrated circuit using the aforementioned method of forming. The invention comprises concurrently forming an isolation trench in an active region and a capacitive trench in an input/output region, concurrently forming a dielectric layer over the walls of the isolation trench and the capacitive trench, and forming a conductive material in the capacitive trench.

Abstract: An integrated circuit (IC) package includes an IC having at least one ESD protection circuit that provides protection against electrostatic discharge. The IC has a plurality of bond pads that are not coupled to the ESD protection circuit. The IC is connected to a substrate. The substrate has a first plurality of conductive traces, which are connected to respective bond pads of the IC, and a second plurality of conductive traces, which are not connected to any of the plurality of bond pads of the IC. Either the substrate or the IC has a common conductive trace that is connected to the ESD protection circuit. Each of the second plurality of conductive traces is connected to the common conductive trace.

Abstract: A process for forming a dual damascene bond pad within an integrated circuit produces a bond pad which is resistant to stress effects and which therefore allows for the bond pad to be formed over active circuitry. The process includes forming a dual damascene structure by forming a bond pad opening having a barrier layer film on the bottom surface of the upper portion of the opening, and forming vias which extend downwardly through the bottom surface. The process produces a bond pad which is resistant to stress effects such as cracking which can be produced when bonding an external wire to the bond pad. Leakage currents between the bond pad and the underlying circuitry are prevented.

Abstract: A semiconductor device comprising a silicon-on-insulator (SOI) substrate including a base substrate, an insulator layer, and a silicon layer, a trench capacitor including at least one trench formed in the silicon-on-insulator substrate and extending through the silicon layer and the insulator layer to the base substrate, and a resistive element formed in the silicon-on-insulator substrate. The capacitor and resistor structure provide an R-C circuit which may be used in triggering an electrostatic discharge (ESD) protection device.

Abstract: A process for forming a dual damascene bond pad within an integrated circuit produces a bond pad which is resistant to stress effects and which therefore allows for the bond pad to be formed over active circuitry. The process includes forming a dual damascene structure by forming a bond pad opening having a barrier layer film on the bottom surface of the upper portion of the opening, and forming vias which extend downwardly through the bottom surface. The process produces a bond pad which is resistant to stress effects such as cracking which can be produced when bonding an external wire to the bond pad. Leakage currents between the bond pad and the underlying circuitry are prevented.

Abstract: In a method of incorporating BIST (built-in self test) circuitry in an integrated circuit, at least one metal layer is arranged to relieve stress in the substrate under bond pads from wire attachment to these pads. By providing at least one stress relieving metal layer, which can be incorporated into electrical paths of the bond pads and related circuitry, BIST circuitry can be provided, at least partly, in the conventionally non-active semiconductive portion of the substrate under the bond pad. The method allows BIST circuitry to occupy conventionally non-active areas under the bond pads wherein leakage current from stress cracks in dielectric layers under the bond pads can be redirected to a metal layer.

Abstract: An integrated circuit and method of use provides conductive vias between conductor layers so that current flows in such a manner that current crowding is reduced in at least one underlying layer. In particular, the current flows from an overlying conductor (306) down to an underlying conductor (303) by a first set of vias (307), and a portion flows through the underlying conductor towards the destination (e.g., a bondpad). Another portion of the current flows downward to a still lower conductor by means of a second set of vias (310, 311). The second set of vias is located further away from the destination than the first set of vias. Current crowding in the underlying conductor is thereby reduced. An integrated circuit utilizing the inventive technique typically has transistors formed in the semiconductor substrate, wherein at least one of the electrodes (e.g.

Abstract: The present invention provides, in one embodiment, an integrated circuit having a substrate and active devices formed on the surface of the substrate. Other embodiments of the integrated circuit provide for having at least either three or four metal layers. In a particular embodiment of the present invention, the integrated circuit comprises a bond pad formed over a portion of the active devices. The bond pad has a footprint. As used therein the word footprint means the area covered by the device to which the word refers. The integrated circuit further incudes a patterned metal layer having a metal layer footprint that is located between the bond pad and the substrate and a built-in self-test (BIST) circuit that has a BIST footprint, which is located between the substrate and the bond pad. In this particular embodiment, the bond pad footprint overlays at least a portion of the metal layer footprint and the BIST footprint.

Abstract: An integrated circuit includes a resistor formed in a doped tub located in a semiconductor substrate. A first highly doped resistor contact region extends outward from the associated contact windows towards a second highly doped resistor contact region. The extent of the underlying tub region that lies between the highly doped tub contact regions largely determines the resistance value. The size and geometry of the highly doped resistor contact regions, and hence the resistance of the resistor, is typically determined by the same mask that defines the thin oxide regions of field effect transistors formed on the IC. In a typical application, the resistor is connected between an output buffer and a bondpad. A multiplicity of output buffers on an IC chip may each connect to corresponding bondpads using a multiplicity of the inventive resistors, which may have the same, or alternatively differing, resistance values.

Abstract: A doped semiconductor distributed resistor is placed in series with the drain of a field effect transistor, typically for electrostatic discharge protection of an integrated circuit. The resistor is defined with a mask formed from the same conductor layer (e.g., polysilicon) that forms the transistor gate conductor. To avoid a floating gate, the conductor mask may be tied to the associated output bondpad. The advantages of using a gate conductor-defined resistor as compared to the prior-art practice includes better control of the resistor dimensions. Hence, the overall size of the output transistor and resistor may be reduced as compared to prior-art techniques, while achieving a high level of ESD protection.

Abstract: Active circuitry is placed under the bond pads in an integrated circuit having at least three metal levels. The metal level adjacent the bond pad level acts as a buffer and provides stress relief and prevents leakage currents between the bond pad and underlying circuitry.

Abstract: CMOS integrated circuit buffers typically use a dual-diode electrostatic discharge (ESD) protection technique. However, in some cases that technique inadvertently causes one of the diodes to conduct when a desired signal voltage is present on the bondpad, thereby clipping the desired signal. This occurs, for example, when an output buffer on an unpowered device is connected to an active bus, or when the input buffer of a 3 volt device receives a 5 volt signal. The present invention solves this problem by using a bipolar (e.g., pnp) protection transistor connected between the bondpad and a power supply bus (e.g., V.sub.SS). The base of the transistor is connected to the bondpad through a resistor that provides a time delay due to the R-C time constant that includes distributed capacitance. The time delay allows for a high conduction period, during which an ESD event is conducted through the bipolar transistor, thereby protecting the input or output buffer.

Abstract: CMOS integrated circuit buffers typically use a dual-diode electrostatic discharge (ESD) protection technique. However, in some cases that technique inadvertently causes one of the diodes to conduct when a desired signal voltage is present on the bondpad, thereby clipping the desired signal. This occurs, for example, when an output buffer on an unpowered device is connected to an active bus, or when the input buffer of a 3 volt device receives a 5 volt signal. The present invention solves this problem by using a bipolar (e.g., pnp) protection transistor connected between the bondpad and a power supply bus (e.g., V.sub.SS). The base of the transistor is connected to the bondpad through a resistor that provides a time delay due to the R-C time constant that includes distributed capacitance. The time delay allows for a high conduction period, during which an ESD event is conducted through the bipolar transistor, thereby protecting the input or output buffer.

Abstract: An integrated circuit obtains improved protection of output buffers against damage from electrostatic discharge (ESD). Each output buffer is connected to its bondpad by means of a resistor, and protective clamping diodes are disposed around the periphery of the bondpad. It has been found that a suitably sized resistor allows the protective diodes to discharge an ESD event before damage to the buffer occurs, by reducing current flow through the buffer, without significantly limiting performance.