Patents by Inventor Yi-Hsiang Huang

Yi-Hsiang Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8871902
    Abstract: POTE has recently been identified as a tumor antigen expressed in a variety of human cancers, including colon, ovarian, breast, prostate, lung and pancreatic cancer. Described herein are immunogenic POTE polypeptides, including modified POTE polypeptides, that bind MHC class I molecules. The immunogenic POTE polypeptides are capable of inducing an immune response against POTE-expressing tumor cells. Thus, provided herein is a method of eliciting an immune response in a subject, such as a subject having a type of cancer that expresses POTE.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: October 28, 2014
    Assignee: The United States of America, as represented by the Secretary, Department of Health and Human Services
    Inventors: Jay A. Berzofsky, Yi-Hsiang Huang, Masaki Terabe, Ira H. Pastan
  • Patent number: 8806301
    Abstract: A data writing method for writing data from a host system into a flash memory chip is provided, and the flash memory chip has a plurality of physical blocks. The method includes receiving a host writing command and write data thereof, and executing the host writing command. The method also includes giving a data program command for writing the write data into one of the physical blocks of the flash memory chip, and giving a command for determining whether data stored in the physical block has any error bit. Accordingly, the method can effectively ensure the correctness of data to be written into the flash memory chip.
    Type: Grant
    Filed: November 19, 2009
    Date of Patent: August 12, 2014
    Assignee: Phison Electronics Corp.
    Inventors: Hsiang-Hsiung Yu, Yi-Hsiang Huang, Chung-Lin Wu, Yu-Chung Shen
  • Publication number: 20140215132
    Abstract: A data writing method, a memory controller, and a memory storage device are provided. The method is applied to control a rewritable non-volatile memory module that includes two memory units. The method includes: configuring a plurality of logical addresses and mapping the logical addresses to at least parts of physical erasing units in the two memory units; receiving a writing command from a host system to instruct to write data into one of the logical addresses; writing the data into a physical erasing unit in the two memory units; determining one of the memory units where the physical erasing unit belongs to; if the physical erasing unit belongs to one of the memory units, erasing another physical erasing unit in the other memory unit while writing the data into the physical erasing unit. Accordingly, a speed of writing data into the memory storage device by the host system is accelerated.
    Type: Application
    Filed: March 15, 2013
    Publication date: July 31, 2014
    Applicant: PHISON ELECTRONICS CORP.
    Inventor: Yi-Hsiang Huang
  • Patent number: 8706952
    Abstract: A flash memory storage device, a controller thereof, and a data programming method are provided. The flash memory storage device has a flash memory comprising a plurality of physical blocks, each physical block includes a plurality of physical addresses, and the physical addresses comprises at least one fast physical address and at least one slow physical address. The method comprises at least grouping the physical blocks into a data area and a spare area; setting a predetermined block number; obtaining m physical blocks from the spare area, receiving a write command comprising a write data and a logical address, determining a logical address range of a buffer according to the logical address and the predetermined block number. When all logical addresses to be programmed with the write data are within the logical address range of the buffer, using a fast mode to program the data into the m physical blocks.
    Type: Grant
    Filed: April 23, 2010
    Date of Patent: April 22, 2014
    Assignee: Phison Electronics Corp.
    Inventors: Chih-Jen Hsu, Yi-Hsiang Huang, Chung-Lin Wu
  • Publication number: 20140040533
    Abstract: A data management method for a rewritable non-volatile memory module including a first memory unit and a second memory unit is provided. The method includes: grouping erasing units of the first memory unit into a data area and a spare area; and grouping the physical erasing units of the second memory unit into a data backup area and a command recording area; configuring multiple logical addresses to map to the physical erasing units associated with the data area; receiving a write command which instructs writing data; writing the data to a physical erasing unit associated with the spare area, and writing the data to a physical erasing unit associated with the data backup area; recording at least a portion of the write command in a physical erasing unit associated with the command recording area. Accordingly, data is backuped in the rewritable non-volatile memory module.
    Type: Application
    Filed: October 2, 2012
    Publication date: February 6, 2014
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Yi-Hsiang Huang, Chao-Ming Chan
  • Publication number: 20140019670
    Abstract: A data writing method for controlling a rewritable non-volatile memory module having physical erasing units is provided. The physical erasing units are grouped into a first buffer area and a second buffer area. A write command instructed to write a data to a first logical address is received. Whether the quantity of the data is smaller than a predetermined value is determined. If so, the data is written into the first buffer area or the second buffer area. If the data is written into the second buffer area, at least one second logical address mapped to at least one physical programing unit in the first buffer area is obtained, and valid data belonging to the second logical address is merged, wherein the number of the second logical address is smaller than a merging threshold. Thereby, the time for a host system to wait for a write success message is shortened.
    Type: Application
    Filed: September 13, 2012
    Publication date: January 16, 2014
    Applicant: PHISON ELECTRONICS CORP.
    Inventor: Yi-Hsiang Huang
  • Patent number: 8452593
    Abstract: A projection apparatus with speech indication and a control method thereof are provided. The projection apparatus comprises a storage unit, a transmission interface, a process unit, and an output unit. The storage unit is configured to store a plurality of speech data. The transmission interface is configured to connect to an external apparatus for accessing the storage unit. The process unit is configured to select at least one of the speech data according to the present state of the projection apparatus. The output unit is configured to output the selected speech datum to broadcast the speech indication.
    Type: Grant
    Filed: August 31, 2007
    Date of Patent: May 28, 2013
    Assignee: Delta Electronics, Inc.
    Inventors: Yi-Hsiang Huang, Yuan Ming Hsu, Jimmy Su
  • Publication number: 20130132640
    Abstract: A data writing method for a rewritable non-volatile memory module, and a memory controller and a memory storage apparatus using the same are provided. The method includes partitioning physical blocks of the rewritable non-volatile memory module into a data area and a spare area and configuring logical blocks. The method also includes selecting physical blocks from the spare area as spare physical blocks corresponding to a logical block and using only lower physical pages of the spare physical blocks to store updated data that is to be written into the logical block. The method further includes moving valid data of all logical pages of the logical block into a physical block of the data area, wherein each lower physical page and an upper physical page corresponding thereto in the physical block are programmed together. Accordingly, the method can effectively improve the speed and reliability of writing data.
    Type: Application
    Filed: February 4, 2012
    Publication date: May 23, 2013
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Chung-Lin Wu, Yi-Hsiang Huang
  • Publication number: 20130039936
    Abstract: POTE has recently been identified as a tumor antigen expressed in a variety of human cancers, including colon, ovarian, breast, prostate, lung and pancreatic cancer. Described herein are immunogenic POTE polypeptides, including modified POTE polypeptides, that bind MHC class I molecules. The immunogenic POTE polypeptides are capable of inducing an immune response against POTE-expressing tumor cells. Thus, provided herein is a method of eliciting an immune response in a subject, such as a subject having a type of cancer that expresses POTE.
    Type: Application
    Filed: September 11, 2012
    Publication date: February 14, 2013
    Inventors: Jay A. Berzofsky, Yi-Hsiang Huang, Masaki Terabe, Ira H. Pastan
  • Patent number: 8255656
    Abstract: A storage device, a memory controller, and a data protection method are provided. The method includes when receiving a read command sent by a host, adopting a corresponding output flow rate limit to determine an operation that is executed on read data corresponding to the read command by the host according to location information included in the read command or a type of a transmission interface between the host and the storage device. The method also includes executing an interference procedure by the storage device to prevent the read data from being copied to the host or slow down the speed of copying the read data to the host when identifying that the operation is a copy operation.
    Type: Grant
    Filed: June 24, 2010
    Date of Patent: August 28, 2012
    Assignee: Phison Electronics Corp.
    Inventors: Hsiang-Hsiung Yu, Chung-Lin Wu, Yi-Hsiang Huang, Yu-Chung Shen
  • Patent number: 8230162
    Abstract: A block management method for managing blocks of a flash memory storage device is provided. The flash memory storage device includes a flash memory controller. The block management method includes the following steps. At least a part of the blocks is grouped into a first partition and a second partition. Whether an authentication code exists is determined. When the authentication code exists, the blocks belonging to the first partition are provided for a host system to access, so the host system displays the first partition and hides the second partition. An authentication information is received from the host system. Whether the authentication information and the authentication code are identical is authenticated. When the authentication information and the authentication code are identical, the blocks belonging to the second partition are provided for the host system to access, so the host system displays the second partition and hides the first partition.
    Type: Grant
    Filed: February 12, 2010
    Date of Patent: July 24, 2012
    Assignee: Phison Electronics Corp.
    Inventors: Hsiang-Hsiung Yu, Yi-Hsiang Huang, Chung-Lin Wu, Yu-Chung Shen
  • Patent number: 8219883
    Abstract: Data accessing method for a flash memory, and a controller and a storage system using the same are provided. The data accessing method includes reading data from a physical address of a flash memory according to a physical address to be read corresponding to a logical address to be read in a read command, and determining whether or not the read physical address is the physical address to be read. The data accessing method also includes transmitting the data only if the read physical address is the physical address to be read. Accordingly, it is possible to ensure the transmitted data is data to be accessed by the read command.
    Type: Grant
    Filed: June 30, 2008
    Date of Patent: July 10, 2012
    Assignee: Phison Electronics Corp.
    Inventors: Chih-Jen Hsu, Yi-Hsiang Huang
  • Publication number: 20120079231
    Abstract: A data writing method and a memory controller and a memory storage apparatus using the same are provided. The data writing method includes grouping a plurality of physical blocks into a plurality of physical units, grouping the physical units into at least a data area and a free area, and configuring a plurality of logical units for mapping to the physical units of the data area. The data writing method also includes getting a physical unit from the free area, writing data in at least one of the logical units into the gotten physical unit, and writing an end mark into the gotten physical unit, and in the gotten physical unit, the end mark follows the data belonging to the at least one logical unit. Thereby, the storage space of each physical unit can be effectively used, and the lifespan of the memory storage apparatus can be prolonged.
    Type: Application
    Filed: November 26, 2010
    Publication date: March 29, 2012
    Applicant: PHISON ELECTRONICS CORP.
    Inventor: Yi-Hsiang Huang
  • Patent number: 8046645
    Abstract: A bad block identifying method for a flash memory, a storage system, and a controller thereof are provided. The bad block identifying method includes determining whether a programming error occurs in a block of the flash memory after the block is programmed and marking the block as a bad block when the programming error successively occurs in the block. Since the block is determined to be a bad block only when the programming error repeatedly occurs in the block, misjudgment of bad block in the flash memory can be avoided and accordingly the lifespan of the flash memory storage system can be prolonged.
    Type: Grant
    Filed: June 16, 2008
    Date of Patent: October 25, 2011
    Assignee: Phison Electronics Corp.
    Inventors: Chih-Jen Hsu, Yi-Hsiang Huang
  • Publication number: 20110191525
    Abstract: A flash memory storage device, a controller thereof, and a data programming method are provided. The flash memory storage device has a flash memory comprising a plurality of physical blocks, each physical block includes a plurality of physical addresses, and the physical addresses comprises at least one fast physical address and at least one slow physical address. The method comprises at least grouping the physical blocks into a data area and a spare area; setting a predetermined block number; obtaining m physical blocks from the spare area, receiving a write command comprising a write data and a logical address, determining a logical address range of a buffer according to the logical address and the predetermined block number. When all logical addresses to be programmed with the write data are within the logical address range of the buffer, using a fast mode to program the data into the m physical blocks.
    Type: Application
    Filed: April 23, 2010
    Publication date: August 4, 2011
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Chih-Jen Hsu, Yi-Hsiang Huang, Chung-Lin Wu
  • Publication number: 20110145482
    Abstract: A block management method for managing blocks of a flash memory storage device is provided. The flash memory storage device includes a flash memory controller. The block management method includes the following steps. At least a part of the blocks is grouped into a first partition and a second partition. Whether an authentication code exists is determined. When the authentication code exists, the blocks belonging to the first partition are provided for a host system to access, so the host system displays the first partition and hides the second partition. An authentication information is received from the host system. Whether the authentication information and the authentication code are identical is authenticated. When the authentication information and the authentication code are identical, the blocks belonging to the second partition are provided for the host system to access, so the host system displays the second partition and hides the first partition.
    Type: Application
    Filed: February 12, 2010
    Publication date: June 16, 2011
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Hsiang-Hsiung Yu, Yi-Hsiang Huang, Chung-Lin Wu, Yu-Chung Shen
  • Publication number: 20110145480
    Abstract: A flash memory storage system including a flash memory chip, a connector, and a controller is provided. The flash memory chip has a plurality of physical blocks. The connector is configured to couple to a host system. The controller is coupled to the flash memory chip and the connector. The controller configures a plurality of logical blocks and maps the logical blocks to a portion of the physical blocks. In addition, the controller identifies rewritable disc commands from the host system and writes data from the host system into the physical blocks mapped to the logical blocks according to the rewritable disc commands. Thereby, a rewritable disc device is simulated by using the flash memory storage system.
    Type: Application
    Filed: January 22, 2010
    Publication date: June 16, 2011
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: HON-WAI NG, Yi-Hsiang Huang, Shih-Hsien Hsu, Hsiang-Hsiung Yu
  • Publication number: 20110087950
    Abstract: A data writing method for writing data from a host system into a flash memory chip is provided, and the flash memory chip have a plurality of physical blocks. The method includes receiving a host writing command and write data thereof, and executing the host writing command. The method also includes giving a data program command for writing the write data into one of the physical blocks to the flash memory chip, and giving a command for determining whether data stored in the physical block has any error bit. Accordingly, the method can effectively ensure the correctness of data to be written into the flash memory chip.
    Type: Application
    Filed: November 19, 2009
    Publication date: April 14, 2011
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Hsiang-Hsiung Yu, Yi-Hsiang Huang, Chung-Lin Wu, Yu-Chung Shen
  • Publication number: 20110066818
    Abstract: A storage device, a memory controller, and a data protection method are provided. The method includes when receiving a read command sent by a host, adopting a corresponding output flow rate limit to determine an operation that is executed on read data corresponding to the read command by the host according to location information included in the read command or a type of a transmission interface between the host and the storage device. The method also includes executing an interference procedure by the storage device to prevent the read data from being copied to the host or slow down the speed of copying the read data to the host when identifying that the operation is a copy operation.
    Type: Application
    Filed: June 24, 2010
    Publication date: March 17, 2011
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Hsiang-Hsiung Yu, Chung-Lin Wu, Yi-Hsiang Huang, Yu-Chung Shen
  • Publication number: 20100149781
    Abstract: An electromagnetic interference shielding apparatus for a signal transceiver comprises a metal cover, a chassis, adhesive, and a waveguide output hole. A first combination portion having a first curved section is disposed on the edge of the metal cover. The first curved section of the first combination portion includes at least one opening The edge of the chassis includes a second combination portion having a groove corresponding to the first combination portion. A lateral slot is at the location of the second combination portion corresponding to the opening The adhesive combines the first combination portion and the second combination portion. A waveguide is disposed in the chassis, and extends to the exterior of the chassis through the waveguide output hole. A flat tool can be inserted into a space between one of the openings and a corresponding lateral slot to separate the metal cover from the chassis.
    Type: Application
    Filed: October 2, 2009
    Publication date: June 17, 2010
    Applicant: MICROELECTRONICS TECHNOLOGY INC.
    Inventors: TE HUA WU, YI HSIANG HUANG