Abstract: An anti-peep light source module includes a light source module and a viewing angle switching module. The light source module has a light source and a light guide plate (LGP) and has light emitting elements arranged along a first direction. The viewing angle switching module is located on a transmission path of an illumination beam of the light source module and includes a viewing angle limiting element and a viewing angle adjusting element configured to change a viewing angle of the illumination beam. The viewing angle limiting element has a grating structure and is located between the viewing angle adjusting element and the light source module. an included angle between an extension direction of the grating structure and the first direction is within a range from 88 degrees to 92 degrees. The anti-peep light source module and A display device achieve favorable optical performance, user experience, and production yield.

Abstract: A device includes a first semiconductor strip and a second semiconductor strip extending longitudinally in a first direction, where the first semiconductor strip and the second semiconductor strip are spaced apart from each other in a second direction. The device also includes a power supply line located between the first semiconductor strip and the second semiconductor strip. A top surface of the power supply line is recessed in comparison to a top surface of the first semiconductor strip. A source feature is disposed on a source region of the first semiconductor strip, and a source contact electrically couples the source feature to the power supply line. The source contact includes a lateral portion contacting a top surface of the source feature, and a vertical portion extending along a sidewall of the source feature towards the power supply line to physically contact the power supply line.

Abstract: An ion implantation system comprising: a sample platform; an ion gun; an electrostatic linear accelerator; a direct current (DC) final energy magnet (FEM); and a processor. The processor is programmed to control: a wafer acceptance test instrument, a DC recipe calculator, a DC real energy calculator, and a tool energy shift verifier. The wafer acceptance test instrument is configured to apply a wafer acceptance test (WAT) recipe to a test sample on the sample platform. The DC recipe calculator is configured to calculate a recipe for the DC FEM. The DC real energy calculator is configured to calculate a real energy of the DC FEM. The tool energy shift verifier is configured to verify a tool energy shift of the DC FEM. The ion implantation system is configured to tune the DC FEM based on the verified tool energy shift, and obtain a peak magnetic field of the DC FEM.

Abstract: A device includes a first semiconductor strip and a second semiconductor strip extending longitudinally in a first direction, where the first semiconductor strip and the second semiconductor strip are spaced apart from each other in a second direction. The device also includes a power supply line located between the first semiconductor strip and the second semiconductor strip. A top surface of the power supply line is recessed in comparison to a top surface of the first semiconductor strip. A source feature is disposed on a source region of the first semiconductor strip, and a source contact electrically couples the source feature to the power supply line. The source contact includes a lateral portion contacting a top surface of the source feature, and a vertical portion extending along a sidewall of the source feature towards the power supply line to physically contact the power supply line.

Abstract: A method for forming a fin field effect transistor device structure is provided. The method includes forming a first spacer layer over a first fin structure and a second fin structure. The method also includes forming a power rail between the first fin structure and the second fin structure. The method further includes forming a second spacer layer over the first spacer layer and the power rail. In addition, the method includes forming a fin isolation structure over the power rail between the first fin structure and the second fin structure. The method also includes forming an epitaxial structure over the first fin structure and the second fin structure. The method further includes forming an inter-layer dielectric structure covering the epitaxial structure. In addition, the method includes forming an opening exposing the epitaxial structure, the power rail and the fin isolation structure. The method also includes filling the opening with a first contact structure.

Abstract: A fin field effect transistor device structure is provided. A fin field effect transistor device structure includes a first fin structure and a second fin structure on a substrate. The fin field effect transistor device structure also includes a spacer layer surrounding the first fin structure and the second fin structure. The fin field effect transistor device structure further includes a power rail over the spacer layer between the first fin structure and the second fin structure. In addition, the fin field effect transistor device structure includes a first contact structure covering the first fin structure and connected to the power rail.

Abstract: A semiconductor structure includes a first semiconductor fin and a second semiconductor fin adjacent to the first semiconductor fin. The first and the second semiconductor fins extend lengthwise along a first direction over a substrate. A metal gate structure is disposed over the first and second semiconductor fins, the metal gate structure extending lengthwise along a second direction perpendicular to the first direction. A first epitaxial source/drain (S/D) feature is disposed over the first semiconductor fin, and a second epitaxial S/D feature is disposed over the second semiconductor fin. An interlayer dielectric (ILD) layer is disposed over the first and the second epitaxial S/D features. And an S/D contact is disposed directly above the first and second epitaxial S/D features. The S/D contact directly contacts the first epitaxial S/D feature, and the S/D contact is isolated from the second epitaxial S/D feature by the ILD layer.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first epitaxial structure and a second epitaxial structure spaced apart from the first epitaxial structure. The semiconductor device structure also includes a conductive contact electrically connected to the first epitaxial structure and a first conductive via over the conductive contact. The semiconductor device structure further includes a second conductive via directly above the second epitaxial structure. The second conductive via is longer than the first conductive via.

Abstract: A structure and a formation method of a semiconductor device are provided. The method includes forming a first source/drain structure and a second source/drain structure over a semiconductor substrate. The method also includes forming a dielectric layer over the first source/drain structure and the second source/drain structure and forming a conductive contact on the first source/drain structure. The method further includes forming a first conductive via over the conductive contact, and the first conductive via is misaligned with the first source/drain structure. In addition, the method includes forming a second conductive via directly above the second source/drain structure, and the second conductive via is longer than the first conductive via.

Abstract: A semiconductor structure includes a first semiconductor fin and a second semiconductor fin adjacent to the first semiconductor fin, a first epitaxial source/drain (S/D) feature disposed over the first semiconductor fin, a second epitaxial S/D feature disposed over the second semiconductor fin, an interlayer dielectric (ILD) layer disposed over the first and the second epitaxial S/D features, and an S/D contact disposed over and contacting the first epitaxial S/D feature, where a portion of the S/D contact laterally extends over the second epitaxial S/D feature, and the portion is separated from the second epitaxial S/D feature by the ILD layer.

Abstract: The present disclosure describes various non-planar semiconductor devices, such as fin field-effect transistors (finFETs) to provide an example, having one or more metal rail conductors and various methods for fabricating these non-planar semiconductor devices. In some situations, the one or more metal rail conductors can be electrically connected to gate, source, and/or drain regions of these various non-planar semiconductor devices. In these situations, the one or more metal rail conductors can be utilized to electrically connect the gate, the source, and/or the drain regions of various non-planar semiconductor devices to other gate, source, and/or drain regions of various non-planar semiconductor devices and/or other semiconductor devices. However, in other situations, the one or more metal rail conductors can be isolated from the gate, the source, and/or the drain regions these various non-planar semiconductor devices.

Abstract: An integrated circuit includes a first and second active region, a first conductive structure, an insulating region, a set of gates and a set of contacts. The first and second active region are in a substrate, extend in a first direction, are located on a first level, and being separated from one another in a second direction. The first conductive structure extends in the first direction, is located on the first level, and is between the first and second active region. The insulating region is located on at least the first level, and is between the first and second active region and the first conductive structure. The set of gates extend in the second direction, overlap the first conductive structure, and is located on a second level. The set of contacts extend in the second direction, overlap the first conductive structure, and is located on the second level.

Abstract: A 3D-IC includes a first tier device and a second tier device. The first tier device and the second tier device are vertically stacked together. The first tier device includes a first substrate and a first interconnect structure formed over the first substrate. The second tier device includes a second substrate, a doped region formed in the second substrate, a dummy gate formed over the substrate, and a second interconnect structure formed over the second substrate. The 3D-IC also includes an inter-tier via extends vertically through the second substrate. The inter-tier via has a first end and a second end opposite the first end. The first end of the inter-tier via is coupled to the first interconnect structure. The second end of the inter-tier via is coupled to one of: the doped region, the dummy gate, or the second interconnect structure.

Abstract: A method for manufacturing a semiconductor product is provided. The method comprises forming a semiconductor device within a wafer utilizing a predetermined number of masks. The method further comprises forming a first low-leakage semiconductor device within the wafer utilizing a first set of additional masks. The first low-leakage semiconductor device has a lower leakage current than that of the semiconductor device.

Abstract: A fin field effect transistor device structure is provided. A fin field effect transistor device structure includes a first fin structure and a second fin structure on a substrate. The fin field effect transistor device structure also includes a spacer layer surrounding the first fin structure and the second fin structure. The fin field effect transistor device structure further includes a power rail over the spacer layer between the first fin structure and the second fin structure. In addition, the fin field effect transistor device structure includes a first contact structure covering the first fin structure and connected to the power rail.

Abstract: An integrated circuit includes a set of active regions in a substrate, a first set of conductive structures, a shallow trench isolation (STI) region, a set of gates and a first set of vias. The set of active regions extend in a first direction and is located on a first level. The first set of conductive structures and the STI region extend in at least the first direction or a second direction, is located on the first level, and is between the set of active regions. The STI region is between the set of active regions and the first set of conductive structures. The set of gates extend in the second direction and overlap the first set of conductive structures. The first set of vias couple the first set of conductive structures to the set of gates.

Abstract: The present disclosure describes various non-planar semiconductor devices, such as fin field-effect transistors (finFETs) to provide an example, having one or more metal rail conductors and various methods for fabricating these non-planar semiconductor devices. In some situations, the one or more metal rail conductors can be electrically connected to gate, source, and/or drain regions of these various non-planar semiconductor devices. In these situations, the one or more metal rail conductors can be utilized to electrically connect the gate, the source, and/or the drain regions of various non-planar semiconductor devices to other gate, source, and/or drain regions of various non-planar semiconductor devices and/or other semiconductor devices. However, in other situations, the one or more metal rail conductors can be isolated from the gate, the source, and/or the drain regions these various non-planar semiconductor devices.

Abstract: An integrated circuit (IC) includes a first p-type semiconductor fin, a first dielectric fin, a first hybrid fin, a second hybrid fin, a second dielectric fin, and a second p-type semiconductor fin disposed in this order along a first direction and oriented lengthwise along a second direction, where each of the first and the second hybrid fins has a first portion including an n-type semiconductor material and a second portion including a dielectric material. The IC further includes n-type source/drain (S/D) epitaxial features disposed over each of the first and the second p-type semiconductor fins, p-type S/D epitaxial features disposed over the first portion of each of the first and the second hybrid fins, and S/D contacts physically contacting each of the p-type S/D epitaxial features and the second portion of each of the first and the second hybrid fins.

Abstract: The present disclosure relates to an integrated circuit. In one implementation, the integrated circuit may include a semiconductor substrate; at least one source region comprising a first doped semiconductor material; at least one drain region comprising a second doped semiconductor material; at least one gate formed between the at least one source region and the at least one drain region; and a nanosheet formed between the semiconductor substrate and the at least one gate. The nanosheet may be configured as a routing channel for the at least one gate and may have a first region having a first width and a second region having a second width. The first width may be smaller than the second width.

Abstract: A static random access memory (SRAM) cell includes a first p-type semiconductor fin, a first dielectric fin, a first hybrid fin, a second hybrid fin, a second dielectric fin, and a second p-type semiconductor fin disposed in this order along a first direction and oriented lengthwise along a second direction, where each of the first and the second hybrid fins has a first portion including an n-type semiconductor material and a second portion including a dielectric material. The SRAM cell further includes n-type source/drain (S/D) epitaxial features disposed over each of the first and the second p-type semiconductor fins, p-type S/D epitaxial features disposed over the first portion of each of the first and the second hybrid fins, and S/D contacts physically contacting each of the p-type S/D epitaxial features and the second portion of each of the first and the second hybrid fins.