Abstract: The present disclosure relates to an integrated circuit. In one implementation, the integrated circuit may include a semiconductor substrate; at least one source region comprising a first doped semiconductor material; at least one drain region comprising a second doped semiconductor material; at least one gate formed between the at least one source region and the at least one drain region; and a nanosheet formed between the semiconductor substrate and the at least one gate. The nanosheet may be configured as a routing channel for the at least one gate and may have a first region having a first width and a second region having a second width. The first width may be smaller than the second width.

Abstract: The present disclosure relates to a method includes generating ions with an ion source of an ion implantation apparatus based on an ion implantation recipe. The method includes accelerating the generated ions based on an ion energy setting in the ion implantation recipe and determining an energy spectrum of the accelerated ions. The method also includes analyzing a relationship between the determined energy spectrum and the ion energy setting. The method further includes adjusting at least one parameter of a final energy magnet (FEM) of the ion implantation apparatus based on the analyzed relationship.

Abstract: An integrated circuit structure is provided including a first transistor, a second transistor, a power rail, a first metal via and a plurality of metal tracks. The first transistor includes a first fin above a substrate and a source feature. The second transistor includes a second fin and a drain feature. The power rail is formed between the first fin and the second fin and below the source feature and the drain feature. The first metal via is formed over the power rail and electrically connected to source or drain feature. The metal tracks are separated from each other. Gaps between any two adjacent metal tracks are identical to each other, each of the metal tracks overlapping the power rail has a first width, each of the metal tracks not overlapping the power rail has a second width, and the first width is greater than the second width.

Abstract: A 3D-IC includes a first tier device and a second tier device. The first tier device and the second tier device are vertically stacked together. The first tier device includes a first substrate and a first interconnect structure formed over the first substrate. The second tier device includes a second substrate, a doped region formed in the second substrate, a dummy gate formed over the substrate, and a second interconnect structure formed over the second substrate. The 3D-IC also includes an inter-tier via extends vertically through the second substrate. The inter-tier via has a first end and a second end opposite the first end. The first end of the inter-tier via is coupled to the first interconnect structure. The second end of the inter-tier via is coupled to one of: the doped region, the dummy gate, or the second interconnect structure.

Abstract: The present disclosure describes various non-planar semiconductor devices, such as fin field-effect transistors (finFETs) to provide an example, having one or more metal rail conductors and various methods for fabricating these non-planar semiconductor devices. In some situations, the one or more metal rail conductors can be electrically connected to gate, source, and/or drain regions of these various non-planar semiconductor devices. In these situations, the one or more metal rail conductors can be utilized to electrically connect the gate, the source, and/or the drain regions of various non-planar semiconductor devices to other gate, source, and/or drain regions of various non-planar semiconductor devices and/or other semiconductor devices. However, in other situations, the one or more metal rail conductors can be isolated from the gate, the source, and/or the drain regions these various non-planar semiconductor devices.

Abstract: An integrated circuit includes a set of active regions in a substrate, a first set of conductive structures, a shallow trench isolation (STI) region, a set of gates and a first set of vias. The set of active regions extend in a first direction and is located on a first level. The first set of conductive structures and the STI region extend in at least the first direction or a second direction, is located on the first level, and is between the set of active regions. The STI region is between the set of active regions and the first set of conductive structures. The set of gates extend in the second direction and overlap the first set of conductive structures. The first set of vias couple the first set of conductive structures to the set of gates.

Abstract: The present disclosure relates to a method includes generating ions with an ion source of an ion implantation apparatus based on an ion implantation recipe. The method includes accelerating the generated ions based on an ion energy setting in the ion implantation recipe and determining an energy spectrum of the accelerated ions. The method also includes analyzing a relationship between the determined energy spectrum and the ion energy setting. The method further includes adjusting at least one parameter of a final energy magnet (FEM) of the ion implantation apparatus based on the analyzed relationship.

Abstract: An air cleaner includes a housing, a fan, one or more filtering elements, and a washing system. The housing is provided with an air inlet and an air outlet. The fan is mounted in the housing at a location corresponding to the air outlet and rotated by a motor. The filtering elements are arranged in the housing below the air outlet while above the air inlet. The washing system includes a drain pan, at least one sprinkler, a water tank and a pump, is located in the housing. The drain pan is provided with a drainage port and obliquely arranged below the filtering elements. The sprinkler is arranged above the filtering elements. The water tank and the pump are mounted at a bottom of the housing. An injection pipe is connected to the water tank and extends out of the housing for filling the water tank with water and/or detergent.

Abstract: A fin field effect transistor device structure includes a first fin structure formed on a substrate. The fin field effect transistor device structure also includes a spacer layer surrounding the first fin structure. The fin field effect transistor device structure further includes a power rail formed over the substrate besides a bottom portion of the first fin structure. The fin field effect transistor device structure further includes a first contact structure formed over the first fin structure and in contact with a portion of the power rail.

Abstract: The present disclosure describes various non-planar semiconductor devices, such as fin field-effect transistors (finFETs) to provide an example, having one or more metal rail conductors and various methods for fabricating these non-planar semiconductor devices. In some situations, the one or more metal rail conductors can be electrically connected to gate, source, and/or drain regions of these various non-planar semiconductor devices. In these situations, the one or more metal rail conductors can be utilized to electrically connect the gate, the source, and/or the drain regions of various non-planar semiconductor devices to other gate, source, and/or drain regions of various non-planar semiconductor devices and/or other semiconductor devices. However, in other situations, the one or more metal rail conductors can be isolated from the gate, the source, and/or the drain regions these various non-planar semiconductor devices.

Abstract: A 3D-IC includes a first tier device and a second tier device. The first tier device and the second tier device are vertically stacked together. The first tier device includes a first substrate and a first interconnect structure formed over the first substrate. The second tier device includes a second substrate, a doped region formed in the second substrate, a dummy gate formed over the substrate, and a second interconnect structure formed over the second substrate. The 3D-IC also includes an inter-tier via extends vertically through the second substrate. The inter-tier via has a first end and a second end opposite the first end. The first end of the inter-tier via is coupled to the first interconnect structure. The second end of the inter-tier via is coupled to one of: the doped region, the dummy gate, or the second interconnect structure.

Abstract: An integrated circuit includes a set of active regions in a substrate, a first set of conductive structures, a shallow trench isolation (STI) region, a set of gates and a first set of vias. The set of active regions extend in a first direction and is located on a first level. The first set of conductive structures and the STI region extend in at least the first direction or a second direction, is located on the first level, and is between the set of active regions. The STI region is between the set of active regions and the first set of conductive structures. The set of gates extend in the second direction and overlap the first set of conductive structures. The first set of vias couple the first set of conductive structures to the set of gates.

Abstract: A method includes providing a substrate comprising a material layer and a hard mask layer; patterning the hard mask layer to form hard mask lines; forming a spacer layer over the substrate, including over the hard mask lines, resulting in trenches defined by the spacer layer, wherein the trenches track the hard mask lines; forming a antireflective layer over the spacer layer, including over the trenches; forming an L-shaped opening in the antireflective layer, thereby exposing at least two of the trenches; filling the L-shaped opening with a fill material; etching the spacer layer to expose the hard mask lines; removing the hard mask lines; after removing the hard mask lines, transferring a pattern of the spacer layer and the fill material onto the material layer, resulting in second trenches tracking the pattern; and filling the second trenches with a conductive material.

Abstract: A method for forming a FinFET device structure includes forming a first fin structure and a second fin structure on a substrate. The method also includes depositing a first spacer layer over the first and second fin structures. The method also includes growing a power rail between the bottom portion of the first fin structure and the bottom portion of the second fin structure. The method also includes forming a second spacer layer over the sidewalls of the first spacer layer and over the top surface of the power rail. The method also includes forming a first fin isolation structure over the power rail between the first and second fin structures. The method also includes forming a first contact structure over the first fin structure and a portion of the power rail. The method also includes forming a second contact structure over the second fin structure.

Abstract: A device includes a first semiconductor strip and a second semiconductor strip extending longitudinally in a first direction, where the first semiconductor strip and the second semiconductor strip are spaced apart from each other in a second direction. The device also includes a power supply line located between the first semiconductor strip and the second semiconductor strip. A top surface of the power supply line is recessed in comparison to a top surface of the first semiconductor strip. A source feature is disposed on a source region of the first semiconductor strip, and a source contact electrically couples the source feature to the power supply line. The source contact includes a lateral portion contacting a top surface of the source feature, and a vertical portion extending along a sidewall of the source feature towards the power supply line to physically contact the power supply line.

Abstract: An integrated circuit structure is provided including a first transistor, a second transistor, a power rail, a first metal via and a plurality of metal tracks. The first transistor includes a first fin above a substrate and a source feature. The second transistor includes a second fin and a drain feature. The power rail is formed between the first fin and the second fin and below the source feature and the drain feature. The first metal via is formed over the power rail and electrically connected to source or drain feature. The metal tracks are separated from each other. Gaps between any two adjacent metal tracks are identical to each other, each of the metal tracks overlapping the power rail has a first width, each of the metal tracks not overlapping the power rail has a second width, and the first width is greater than the second width.

Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming a fin structure on a substrate; forming a dummy gate over the fin structure; forming spacers on sides of the dummy gate; forming a doped region within the fin structure; replacing the dummy gate with a metal gate; replacing an upper portion of the metal gate with a first dielectric layer; forming a conductive layer directly on the doped region; replacing an upper portion of the conductive layer with a second dielectric layer; removing the first dielectric layer thereby exposing a sidewall of the spacer; removing an upper portion of the spacer to thereby expose a sidewall of the second dielectric layer; removing at least a portion of the second dielectric layer to form a trench; and forming a conductive plug in the trench.

Abstract: A method includes providing a substrate comprising a material layer and a hard mask layer; patterning the hard mask layer to form hard mask lines; forming a spacer layer over the substrate, including over the hard mask lines, resulting in trenches defined by the spacer layer, wherein the trenches track the hard mask lines; forming a antireflective layer over the spacer layer, including over the trenches; forming an L-shaped opening in the antireflective layer, thereby exposing at least two of the trenches; filling the L-shaped opening with a fill material; etching the spacer layer to expose the hard mask lines; removing the hard mask lines; after removing the hard mask lines, transferring a pattern of the spacer layer and the fill material onto the material layer, resulting in second trenches tracking the pattern; and filling the second trenches with a conductive material.

Abstract: A method for forming a FinFET device structure includes forming a first fin structure and a second fin structure on a substrate. The method also includes depositing a first spacer layer over the first and second fin structures. The method also includes growing a power rail between the bottom portion of the first fin structure and the bottom portion of the second fin structure. The method also includes forming a second spacer layer over the sidewalls of the first spacer layer and over the top surface of the power rail. The method also includes forming a first fin isolation structure over the power rail between the first and second fin structures. The method also includes forming a first contact structure over the first fin structure and a portion of the power rail. The method also includes forming a second contact structure over the second fin structure.

Abstract: A static random access memory (SRAM) cell includes a first p-type semiconductor fin, a first dielectric fin, a first hybrid fin, a second hybrid fin, a second dielectric fin, and a second p-type semiconductor fin disposed in this order along a first direction and oriented lengthwise along a second direction, where each of the first and the second hybrid fins has a first portion including an n-type semiconductor material and a second portion including a dielectric material. The SRAM cell further includes n-type source/drain (S/D) epitaxial features disposed over each of the first and the second p-type semiconductor fins, p-type S/D epitaxial features disposed over the first portion of each of the first and the second hybrid fins, and S/D contacts physically contacting each of the p-type S/D epitaxial features and the second portion of each of the first and the second hybrid fins.