Abstract: A method and structure for forming a local interconnect, without routing the local interconnect through an overlying metal layer. In various embodiments, a first dielectric layer is formed over a gate stack of at least one device and a second dielectric layer is formed over a contact metal layer of the at least one device. In various embodiments, a selective etching process is performed to remove the second dielectric layer and expose the contact metal layer, without substantial removal of the first dielectric layer. In some examples, a metal VIA layer is deposited over the at least one device. The metal VIA layer contacts the contact metal layer and provides a local interconnect structure. In some embodiments, a multi-level interconnect network overlying the local interconnect structure is formed.

Abstract: A method of forming a set of masks for manufacturing an integrated circuit includes determining a presence of a first via layout pattern and a power rail layout pattern in an original layout design. The first via layout pattern and the power rail layout pattern overlap each other. The first via layout pattern is part of a first cell layout of the original layout design. The power rail layout pattern is shared by the first cell layout and a second cell layout of the original layout design. The method further includes modifying the original layout design to become a modified layout design and forming the set of masks based on the modified layout design. The modifying the original layout design includes, if the first via layout pattern and the power rail are present in the original layout design, replacing the first via layout pattern with an enlarged via layout pattern.

Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming a fin structure on a substrate; forming a dummy gate over the fin structure; forming spacers on sides of the dummy gate; forming a doped region within the fin structure; replacing the dummy gate with a metal gate; replacing an upper portion of the metal gate with a first dielectric layer; forming a conductive layer directly on the doped region; replacing an upper portion of the conductive layer with a second dielectric layer; removing the first dielectric layer thereby exposing a sidewall of the spacer; removing an upper portion of the spacer to thereby expose a sidewall of the second dielectric layer; removing at least a portion of the second dielectric layer to form a trench; and forming a conductive plug in the trench.

Abstract: A 3D-IC includes a first tier device and a second tier deice. The first tier device and the second tier device are vertically stacked together. The first tier device includes a first substrate and a first connect structure formed over the first substrate. The second tier device includes a second substrate, a doped region formed in the second substrate, a dummy gate formed over the substrate, and a second interconnect structure formed over the second substrate. The 3D-IC also includes an inter-tier via extends vertically through the second substrate. The inter-tier via has a first end and a second end opposite the first end. The first end of the inter-tier via is coupled to the first interconnect structure. The second end of the inter-tier via is coupled to one of: the doped region, the dummy gate, or the second interconnect structure.

Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming a fin structure on a substrate; forming a dummy gate over the fin structure; forming spacers on sides of the dummy gate; forming a doped region within the fin structure; replacing the dummy gate with a metal gate; replacing an upper portion of the metal gate with a first dielectric layer; forming a conductive layer directly on the doped region; replacing an upper portion of the conductive layer with a second dielectric layer; removing the first dielectric layer thereby exposing a sidewall of the spacer; removing an upper portion of the spacer to thereby expose a sidewall of the second dielectric layer; removing at least a portion of the second dielectric layer to form a trench; and forming a conductive plug in the trench.

Abstract: A 3D-IC includes a first tier device and a second tier device. The first tier device and the second tier device are vertically stacked together. The first tier device includes a first substrate and a first interconnect structure formed over the first substrate. The second tier device includes a second substrate, a doped region formed in the second substrate, a dummy gate formed over the substrate, and a second interconnect structure formed over the second substrate. The 3D-IC also includes an inter-tier via extends vertically through the second substrate. The inter-tier via has a first end and a second end opposite the first end. The first end of the inter-tier via is coupled to the first interconnect structure. The second end of the inter-tier via is coupled to one of: the doped region, the dummy gate, or the second interconnect structure.

Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming a fin structure on a substrate; forming a dummy gate over the fin structure; forming spacers on sides of the dummy gate; forming a doped region within the fin structure; replacing the dummy gate with a metal gate; replacing an upper portion of the metal gate with a first dielectric layer; forming a conductive layer directly on the doped region; replacing an upper portion of the conductive layer with a second dielectric layer; removing the first dielectric layer thereby exposing a sidewall of the spacer; removing an upper portion of the spacer to thereby expose a sidewall of the second dielectric layer; removing at least a portion of the second dielectric layer to form a trench; and forming a conductive plug in the trench.

Abstract: A 3D-IC includes a first tier device and a second tier device. The first tier device and the second tier device are vertically stacked together. The first tier device includes a first substrate and a first interconnect structure formed over the first substrate. The second tier device includes a second substrate, a doped region formed in the second substrate, a dummy gate formed over the substrate, and a second interconnect structure formed over the second substrate. The 3D-IC also includes an inter-tier via extends vertically through the second substrate. The inter-tier via has a first end and a second end opposite the first end. The first end of the inter-tier via is coupled to the first interconnect structure. The second end of the inter-tier via is coupled to one of: the doped region, the dummy gate, or the second interconnect structure.

Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming a first gate structure over a substrate, forming a source/drain feature in the substrate adjacent the first gate structure, forming a dielectric layer over the first gate structure and the source/drain feature, removing a portion of the dielectric layer to form a first trench exposing the first gate structure and the source/drain feature, forming a first conductive feature in the first trench, removing a first portion of the first gate structure to form a second trench and forming a second conductive feature in the second trench.

Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming a first gate structure over a substrate, forming a source/drain feature in the substrate adjacent the first gate structure, forming a dielectric layer over the first gate structure and the source/drain feature, removing a portion of the dielectric layer to form a first trench exposing the first gate structure and the source/drain feature, forming a first conductive feature in the first trench, removing a first portion of the first gate structure to form a second trench and forming a second conductive feature in the second trench.

Abstract: Vertical gate all-around (VGAA) structures are described. In an embodiment, a structure including a first doped region in a substrate, a first vertical channel extending from the first doped region, a first metal-semiconductor compound region in a top surface of the first doped region, the first metal-semiconductor compound region extending along at least two sides of the first vertical channel, and a first gate electrode around the first vertical channel.

Abstract: A method of forming a set of masks for manufacturing an integrated circuit includes determining a presence of a first via layout pattern and a power rail layout pattern in an original layout design. The first via layout pattern and the power rail layout pattern overlap each other. The first via layout pattern is part of a first cell layout of the original layout design. The power rail layout pattern is shared by the first cell layout and a second cell layout of the original layout design. The method further includes modifying the original layout design to become a modified layout design and forming the set of masks based on the modified layout design. The modifying the original layout design includes, if the first via layout pattern and the power rail are present in the original layout design, replacing the first via layout pattern with an enlarged via layout pattern.

Abstract: Systems and methods are provided for ion implantation. For example, ion implantation is performed using a first ion implant tool. At least one condition parameter associated with the first ion implant tool is dynamically obtained. Whether the first ion implant tool is in a first condition is determined based on the at least one condition parameter. Ion implantation is performed using a second ion implant tool based on the determination.

Abstract: Systems and methods are provided for ion implantation. For example, ion implantation is performed using a first ion implant tool. At least one condition parameter associated with the first ion implant tool is dynamically obtained. Whether the first ion implant tool is in a first condition is determined based on the at least one condition parameter. Ion implantation is performed using a second ion implant tool based on the determination.

Abstract: A semiconductor structure and method of manufacturing the semiconductor structure, and more particularly to a semiconductor structure having reduced metal line resistance and a method of manufacturing the same in back end of line (BEOL) processes. The method includes forming a first trench extending to a lower metal layer Mx+1 and forming a second trench remote from the first trench. The method further includes filling the first trench and the second trench with conductive material. The conductive material in the second trench forms a vertical wiring line extending orthogonally and in electrical contact with an upper wiring layer and electrically isolated from lower metal layers including the lower metal layer Mx+1. The vertical wiring line decreases a resistance of a structure.

Abstract: An indoor air conditioner able to carry out washing and cleaning automatically includes a housing having a separating plate bored with wind outlets and through holes. Two fans are respectively received in two fan-accommodating grooves of the housing; a motor is installed in a motor-accommodating groove, having two rotary shafts respectively connected with the fan and covered with a waterproof bushing. Two filter screens are respectively assembled in the fan-accommodating groove; a heat exchanger is received in a heat exchanger-accommodating groove. The housing has one sidewall bored with a water intake, a water exhaust port and an overflow port. An upper cover is provided with a wind intake and a wind outlet, having a wind intake guide plate installed with disinfecting lamps, and further bored with a filling port and an exhaust port for refrigerant, ice water or hot water, a detergent filling pipe and an external air duct.

Abstract: A semiconductor structure and method of manufacturing the semiconductor structure, and more particularly to a semiconductor structure having reduced metal line resistance and a method of manufacturing the same in back end of line (BEOL) processes. The method includes forming a first trench extending to a lower metal layer Mx+1 and forming a second trench remote from the first trench. The method further includes filling the first trench and the second trench with conductive material. The conductive material in the second trench forms a vertical wiring line extending orthogonally and in electrical contact with an upper wiring layer and electrically isolated from lower metal layers including the lower metal layer Mx+1. The vertical wiring line decreases a resistance of a structure.

Abstract: A semiconductor structure and method of manufacturing the semiconductor structure, and more particularly to a semiconductor structure having reduced metal line resistance and a method of manufacturing the same in back end of line (BEOL) processes. The method includes forming a first trench extending to a lower metal layer Mx+1 and forming a second trench remote from the first trench. The method further includes filling the first trench and the second trench with conductive material. The conductive material in the second trench forms a vertical wiring line extending orthogonally and in electrical contact with an upper wiring layer and electrically isolated from lower metal layers including the lower metal layer Mx+1. The vertical wiring line decreases a resistance of a structure.

Abstract: A cooler includes a body, a water tank installed in the body for storing cooling water, a pump fixed in the water tank, a water pipe connected to the pump and extending upward, a spray pipe connected to the water pipe, at least one gas cooling device located above the spray pipe, at least one fan fixed on top of the body, at least one wind hole formed in a side of the body, at least one cooling pipe uprightly installed in the body and having an upper portion passing through heat-dispersing chips of the gas cooling device and a lower portion passing through heat-dispersing chips of the water cooling device, and at least one water-heat exchanger below the spray pipe and having a heat-dispersing element. The cooler has two stages of cooling by air and water, having a high effect of swift cooling high temperature to low temperature.

Abstract: A cooler includes a body, a water tank installed in the body for storing cooling water, a pump fixed in the water tank, a water pipe connected to the pump and extending upward, a spray pipe connected to the water pipe, at least one gas cooling device located above the spray pipe, at least one fan fixed on top of the body, at least one wind hole formed in a side of the body, at least one cooling pipe uprightly installed in the body and having an upper portion passing through heat-dispersing chips of the gas cooling device and a lower portion passing through heat-dispersing chips of the water cooling device, and at least one water-heat exchanger below the spray pipe and having a heat-dispersing element. The cooler has two stages of cooling by air and water, having a high effect of swift cooling high temperature to low temperature.