Abstract: Embodiments of the present disclosure relate to methods for positioning masks in a propagation direction of a light source. The masks correspond to a pattern to be written into a photoresist layer of a substrate. The masks are positioned by stitching a first mask and a second mask. The first mask includes a set of first features having first feature extensions extending therefrom at first feature interfaces. The second mask includes a set of second features having second feature extensions extending therefrom at second feature interfaces. Each first feature extension stitches with each corresponding second feature extension to form each stitched portion of a first stitched portion of the first pair of masks. The stitched portion of the first pair of masks defines a portion of the pattern to be written into the photoresist layer.

Abstract: A method of forming patterned features on a substrate is provided. The method includes positioning a plurality of masks arranged in a mask layout over a substrate. The substrate is positioned in a first plane and the plurality of masks are positioned in a second plane, the plurality of masks in the mask layout have edges that each extend parallel to the first plane and parallel or perpendicular to an alignment feature on the substrate, the substrate includes a plurality of areas configured to be patterned by energy directed through the masks arranged in the mask layout. The method further includes directing energy towards the plurality of areas through the plurality of masks arranged in the mask layout over the substrate to form a plurality of patterned features in each of the plurality of areas.

Abstract: A semiconductor device includes a stack structure having at least first, second and third interconnect levels. Each interconnect level has a patterned metal conductor including a first metallic material. A via spans the second and third interconnect levels and electrically couples with the patterned metal conductor of the first interconnect level. At least a segment of the super via includes a second metallic material different from the first metallic material.

Abstract: Aspects of the present disclosure relate generally to methods and apparatus of processing transparent substrates, such as glass substrates. In one implementation, a film stack for optical devices includes a glass substrate including a first surface and a second surface. The film stack includes a device function layer formed on the first surface, a hard mask layer formed on the device function layer, and a substrate recognition layer formed on the hard mask layer. The hard mask layer includes one or more of chromium, ruthenium, or titanium nitride. The film stack includes a backside layer formed on the second surface. The backside layer formed on the second surface includes one or more of a conductive layer or an oxide layer.

Abstract: A semiconductor device includes at least one mandrel including a dielectric material, and at least one non-mandrel including a hard mask material having an etch property substantially similar to that of the dielectric material.

Abstract: First lithography and etching are carried out on a semiconductor structure to provide a first intermediate semiconductor structure having a first set of surface features corresponding to a first portion of desired fin formation mandrels. Second lithography and etching are carried out on the first intermediate structure, using a second mask, to provide a second intermediate semiconductor structure having a second set of surface features corresponding to a second portion of the mandrels. The second set of surface features are unequally spaced from the first set of surface features and/or the features have different pitch. The fin formation mandrels are formed in the second intermediate semiconductor structure using the first and second sets of surface features; spacer material is deposited over the mandrels and is etched back to form a third intermediate semiconductor structure having a fin pattern. Etching is carried out on same to produce the fin pattern.

Abstract: A method of increasing production of one or more lipoxins in a subject in need thereof comprising administering to the subject an amount of a compound having the structure: or a pharmaceutically acceptable salt or ester thereof, so as to thereby increase production of the one or more lipoxins in the subject.

Abstract: A method for fabricating a semiconductor device includes forming first and second interconnect levels on a substrate with the first and second interconnect levels having respective first and second dielectric layers and first and second patterned metal conductors and where each of the first and second patterned metal conductors includes a first metallic material, depositing a third dielectric layer onto the second first interconnect layer, forming a via opening extending through the third dielectric layer and the second dielectric layer and connecting with the first patterned metal conductor of the first interconnect level and depositing a second metallic material different from the first metallic material into the via opening to form a via The via electrically couples with the patterned metal layer of the first interconnect level.

Abstract: A method of removing layers of an extreme ultraviolet (EUV) pattern stack is provided. The method includes forming one or more resist templates on an upper hardmask layer. The method further includes exposing portions of the surface of the upper hardmask layer to a dry etch process to produce modified and activated surfaces. The method further includes etching the modified and activated surfaces to expose an underlying organic planarization layer.

Abstract: Aspects of the present disclosure relate generally to methods and apparatus of processing transparent substrates, such as glass substrates. In one implementation, a film stack for optical devices includes a glass substrate including a first surface and a second surface. The film stack includes a device function layer formed on the first surface, a hard mask layer formed on the device function layer, and a substrate recognition layer formed on the hard mask layer. The hard mask layer includes one or more of chromium, ruthenium, or titanium nitride. The film stack includes a backside layer formed on the second surface. The backside layer formed on the second surface includes one or more of a conductive layer or an oxide layer.

Abstract: Aspects of the present disclosure relate generally to methods and apparatus of processing transparent substrates, such as glass substrates. In one implementation, a film stack for optical devices includes a glass substrate including a first surface and a second surface. The film stack includes a device function layer formed on the first surface, a hard mask layer formed on the device function layer, and a substrate recognition layer formed on the hard mask layer. The hard mask layer includes one or more of chromium, ruthenium, or titanium nitride. The film stack includes a backside layer formed on the second surface. The backside layer formed on the second surface includes one or more of a conductive layer or an oxide layer.

Abstract: In one embodiment, a method of fabricating a device having at least two features of differing heights comprises: depositing a resist over a substrate; determining a topography pattern for the at least two features of the device; determining an exposure pattern for the at least two features of the device; exposing a first area of the resist with a first dose of light, the first area corresponding to a first feature of the at least two features; exposing a second area of the resist with a second dose of light that is different from the first dose of light, the second area corresponding to a second feature of the at least two features; and developing the resist.

Abstract: Embodiments of the present disclosure relate to methods for positioning masks in a propagation direction of a light source. The masks correspond to a pattern to be written into a photoresist layer of a substrate. The masks are positioned by stitching a first mask and a second mask. The first mask includes a set of first features having first feature extensions extending therefrom at first feature interfaces. The second mask includes a set of second features having second feature extensions extending therefrom at second feature interfaces. Each first feature extension stitches with each corresponding second feature extension to form each stitched portion of a first stitched portion of the first pair of masks. The stitched portion of the first pair of masks defines a portion of the pattern to be written into the photoresist layer.

Abstract: A technique relates to a semiconductor device. Mandrels are formed on a substrate, the mandrels including a first metal layer. A second metal layer is formed on the substrate adjacent to the first metal layer, the first and second metal layers being separated by spacer material.

Abstract: First lithography and etching are carried out on a semiconductor structure to provide a first intermediate semiconductor structure having a first set of surface features corresponding to a first portion of desired fin formation mandrels. Second lithography and etching are carried out on the first intermediate structure, using a second mask, to provide a second intermediate semiconductor structure having a second set of surface features corresponding to a second portion of the mandrels. The second set of surface features are unequally spaced from the first set of surface features and/or the features have different pitch. The fin formation mandrels are formed in the second intermediate semiconductor structure using the first and second sets of surface features; spacer material is deposited over the mandrels and is etched back to form a third intermediate semiconductor structure having a fin pattern. Etching is carried out on same to produce the fin pattern.

Abstract: A method of forming patterned features on a substrate is provided. The method includes positioning a plurality of masks arranged in a mask layout over a substrate. The substrate is positioned in a first plane and the plurality of masks are positioned in a second plane, the plurality of masks in the mask layout have edges that each extend parallel to the first plane and parallel or perpendicular to an alignment feature on the substrate, the substrate includes a plurality of areas configured to be patterned by energy directed through the masks arranged in the mask layout. The method further includes directing energy towards the plurality of areas through the plurality of masks arranged in the mask layout over the substrate to form a plurality of patterned features in each of the plurality of areas.

Abstract: Embodiments of the present disclosure relate to bake apparatuses for handling and uniform baking of substrates and methods for the handling and the uniform baking of substrates. The bake apparatuses allow the substrates to be heated to a temperature greater than 50° C. without bowing of about 1 mm to about 2 mm from the edge of the substrates to the center of the substrates. The bake apparatuses heat the substrates uniformly or substantially uniformly to improve substrate quality.

Abstract: Selective gas etching for self-aligned pattern transfer uses a first block and a separate second block formed in a sacrificial layer to transfer critical dimensions to a desired final layer using a selective gas etching process. The first block is a first hardmask material that can be plasma etched using a first gas, and the second block is a second hardmask material that can be plasma etched using a second gas separate from the first gas. The first hardmask material is not plasma etched using the second gas, and the second hardmask material is not plasma etched using the first gas.

Abstract: A method is presented for forming interlayer connections in a semiconductor device. The method includes patterning an etch stack to provide for a plurality of interlayer connections, etching guide layers following the etch stack to a first capping layer to form a plurality of guide openings, concurrently exposing a first plurality of conductive lines and a second plurality of conductive lines to form a plurality of interlayer connection openings by etching through the plurality of guide openings to remove the first capping layer, an interlayer dielectric, and a second capping layer, and depositing a metal fill in the plurality of interlayer connection openings to form the plurality of interlayer connections.

Abstract: A method is presented for amplifying extreme ultraviolet (EUV) lithography pattern transfer into a hardmask and preventing hard mask micro bridging effects due to resist residue in a semiconductor structure. The method includes forming a top hardmask over an organic planarization layer (OPL), depositing a photoresist over the top hardmask, patterning the photoresist using EUV lithography, performing ion implantation to create doped regions within the exposed top hardmask and regions of hardmask underneath resist residue, stripping the photoresist, and selectively etching the top hardmask by either employing positive tone or negative tone etch based on an implantation material.