Abstract: Disclosed are embodiments of a multi-layer stack and photolithography methods and systems that employ such a stack. The disclosed multi-layer stacks include a photoresist layer on an underlayer. The photoresist layer and underlayer are made of different materials, which are selected so that valence and conduction band offsets between the underlayer and photoresist layer create an effective electric field (i.e., so that the stack is “self-biased”). When areas of the photoresist layer are exposed to radiation during photolithography and the radiation passes through photoresist layer and excites electrons in the underlayer, this effective electric field facilitates movement of the radiation-excited electrons from the underlayer into the radiation-exposed areas of the photoresist layer in a direction normal to the interface between the underlayer and the photoresist layer.

Abstract: Techniques for generating enhanced inductors and other electronic devices are presented. A device generator component (DGC) performs directed-self assembly (DSA) co-polymer deposition on a circular guide pattern formed in low-k dielectric film, and DSA annealing to form two polymers in the form of alternating concentric rings; performs a loop cut in the concentric rings to form concentric segments; fills the cut portion with insulator material; selectively removes first polymer, fills the space with low-k dielectric, and planarizes the surface; selectively removes the second polymer, fills the space with conductive material, and planarizes the surface; deposits low-k film on top of the concentric segments and insulator material that filled the loop cut portion; forms vias in the low-k film, wherein each via spans from an end of one segment to an end of another segment; and fills vias with conductive material to form conductive connectors to form substantially spiral conductive structure.

Abstract: First lithography and etching are carried out on a semiconductor structure to provide a first intermediate semiconductor structure having a first set of surface features corresponding to a first portion of desired fin formation mandrels. Second lithography and etching are carried out on the first intermediate structure, using a second mask, to provide a second intermediate semiconductor structure having a second set of surface features corresponding to a second portion of the mandrels. The second set of surface features are unequally spaced from the first set of surface features and/or the features have different pitch. The fin formation mandrels are formed in the second intermediate semiconductor structure using the first and second sets of surface features; spacer material is deposited over the mandrels and is etched back to form a third intermediate semiconductor structure having a fin pattern. Etching is carried out on same to produce the fin pattern.

Abstract: Embodiments of the present invention are directed to techniques for forming a vertical field effect transistor (VFET) top spacer using an area selective cyclic deposition. In a non-limiting embodiment of the invention, a first semiconductor fin is formed over a substrate. A second semiconductor fin is formed over the substrate and adjacent to the first semiconductor fin. A dielectric isolation region is formed between the first semiconductor fin and the second semiconductor fin. A top spacer is formed between the first semiconductor fin and the second semiconductor fin by cyclically depositing dielectric layers over the dielectric isolation region. The dielectric layers are inhibited from depositing on a surface of the first semiconductor fin and on a surface of the second semiconductor fin during the cyclic deposition process.

Abstract: A method is presented for amplifying extreme ultraviolet (EUV) lithography pattern transfer into a hardmask and preventing hard mask micro bridging effects due to resist residue in a semiconductor structure. The method includes forming a top hardmask over an organic planarization layer (OPL), depositing a photoresist over the top hardmask, patterning the photoresist using EUV lithography, performing ion implantation to create doped regions within the exposed top hardmask and regions of hardmask underneath resist residue, stripping the photoresist, and selectively etching the top hardmask by either employing positive tone or negative tone etch based on an implantation material.

Abstract: A method of making a semiconductor device includes depositing an oxide material on a patterned mask arranged on a substrate. The method further includes removing a portion of the oxide material such that the patterned mask is exposed. The method also includes removing the patterned mask such that the substrate is exposed between areas of remaining oxide material.

Abstract: An Nblock layer is deposited onto a semiconductor substrate that includes metal deposits. A titanium nitride (TiN) layer is deposited directly onto the Nblock layer; an oxide layer is deposited directly onto the TiN layer; and a via hole is formed through the oxide and TiN layer to contact bottom interconnect. The via hole is aligned to one of the metal deposits in the substrate.

Abstract: A mechanism for preparing a wafer and/or substrate is disclosed. A plurality of mandrel lines are etched via a mandrel mask. The mandrel lines are separated by spaces. Spin-on glass (SOG) is deposited to backfill the spaces between the mandrel lines. A non-mandrel mask is employed to etch spaces from the SOG in between the mandrel lines to create non-mandrel lines. The mandrel lines and the non-mandrel lines can then be replaced with a conductive material.

Abstract: A method for manufacturing a semiconductor device includes forming a first interconnect level having a conductive metal layer formed in a first dielectric layer. In the method, a cap layer is formed on the first interconnect level, and a second interconnect level including a second dielectric layer is formed on the cap layer. The method also includes forming a third interconnect level including a third dielectric layer on the second interconnect level. An opening is formed through the second and third interconnect levels and over the conductive metal layer. Sides of the opening are lined with a spacer material, and a portion of the cap layer at a bottom of the opening is removed from a top surface of the conductive metal layer. The spacer material is removed from the opening, and a conductive material layer is deposited in the opening on the conductive metal layer.

Abstract: Extreme ultraviolet (EUV) lithographic patterning methods are provided which implement directional deposition on the EUV resist mask to improve selectivity and critical dimension control during the patterning of features in multiple layers. A hard mask material is deposited on a substrate structure using directional deposition. The hard mask material forms a hard mask layer that covers patterning features of an EUV resist mask of the substrate structure. The hard mask material is etched selective to a layer underlying the EUV resist mask to remove portions of the hard mask material that were deposited on the underlying layer during the directional deposition without uncovering the patterning features of the EUV resist mask. At least one layer of the substrate structure is patterned based on the EUV resist mask and the hard mask layer.

Abstract: A method is presented for amplifying extreme ultraviolet (EUV) lithography pattern transfer into a hardmask and preventing hard mask micro bridging effects due to resist residue in a semiconductor structure. The method includes forming a top hardmask over an organic planarization layer (OPL), depositing a photoresist over the top hardmask, patterning the photoresist using EUV lithography, performing ion implantation to create doped regions within the exposed top hardmask and regions of hardmask underneath resist residue, stripping the photoresist, and selectively etching the top hardmask by either employing positive tone or negative tone etch based on an implantation material.

Abstract: A method is presented for amplifying extreme ultraviolet (EUV) lithography pattern transfer into a hardmask and preventing hard mask micro bridging effects due to resist scumming in a semiconductor structure. The method includes forming a top hardmask over an organic planarization layer (OPL), depositing a photoresist over the top hardmask, patterning the photoresist using EUV lithography, performing ion implantation to create doped regions within the exposed top hardmask and regions of hardmask underneath resist scumming, stripping the photoresist, and selectively etching the top hardmask by either employing positive tone or negative tone etch based on an implantation material.

Abstract: Embodiments of the present invention are directed to techniques for forming a vertical field effect transistor (VFET) top spacer using an area selective cyclic deposition. In a non-limiting embodiment of the invention, a first semiconductor fin is formed over a substrate. A second semiconductor fin is formed over the substrate and adjacent to the first semiconductor fin. A dielectric isolation region is formed between the first semiconductor fin and the second semiconductor fin. A top spacer is formed between the first semiconductor fin and the second semiconductor fin by cyclically depositing dielectric layers over the dielectric isolation region. The dielectric layers are inhibited from depositing on a surface of the first semiconductor fin and on a surface of the second semiconductor fin during the cyclic deposition process.

Abstract: A method for providing an etch mask for microelectronic processing that includes forming a material stack on a surface to be etched, wherein the material stack of at least a first material layer atop the surface to be etched for a base mandrel layer, and a second material layer atop the first material layer to provide a cap mandrel layer. If a following step, the material stack may be patterned and etched to provide double mandrel structures each including said base mandrel layer and said cap mandrel layer. A sidewall spacer is formed on sidewalls of the double mandrel structures.

Abstract: A method for manufacturing a semiconductor device includes forming a first interconnect level having a conductive metal layer formed in a first dielectric layer. In the method, a cap layer is formed on the first interconnect level, and a second interconnect level including a second dielectric layer is formed on the cap layer. The method also includes forming a third interconnect level including a third dielectric layer on the second interconnect level. An opening is formed through the second and third interconnect levels and over the conductive metal layer. Sides of the opening are lined with a spacer material, and a portion of the cap layer at a bottom of the opening is removed from a top surface of the conductive metal layer. The spacer material is removed from the opening, and a conductive material layer is deposited in the opening on the conductive metal layer.

Abstract: An Nblock layer is deposited onto a semiconductor substrate that includes metal deposits. A titanium nitride (TiN) layer is deposited directly onto the Nblock layer; an oxide layer is deposited directly onto the TiN layer; and a via hole is formed through the oxide and TiN layer to contact bottom interconnect. The via hole is aligned to one of the metal deposits in the substrate.

Abstract: Extreme ultraviolet (EUV) lithographic patterning methods are provided which implement directional deposition on the EUV resist mask to improve selectivity and critical dimension control during the patterning of features in multiple layers. A hard mask material is deposited on a substrate structure using directional deposition. The hard mask material forms a hard mask layer that covers patterning features of an EUV resist mask of the substrate structure. The hard mask material is etched selective to a layer underlying the EUV resist mask to remove portions of the hard mask material that were deposited on the underlying layer during the directional deposition without uncovering the patterning features of the EUV resist mask. At least one layer of the substrate structure is patterned based on the EUV resist mask and the hard mask layer.

Abstract: Semiconductor structures fabricated via extreme ultraviolet (EUV) lithographic patterning techniques implementing directional deposition on a EUV resist mask improves selectivity and critical dimension control during the patterning of features in multiple layers of the semiconductor substrate. A semiconductor structure includes a substrate structure having an extreme ultraviolet resist mask disposed over one or more additional layers of the substrate structure. The extreme ultraviolet resist mask defines patterning features. A hard mask layer including a hard mask material is disposed on the extreme ultraviolet resist mask and covers the patterning features of the extreme ultraviolet resist mask.

Abstract: Embodiments of the invention include methods and structures for controlling developer critical dimension (DCD) variations across a wafer surface. Aspects of the invention include an apparatus having developer tubing and an internal cam. The internal cam is coupled to a fixed axis. A flexible divider is positioned between the developer tubing and the internal cam. The flexible divider is coupled to the internal cam such that rotation of the internal cam about the fixed axis is operable to change an inner diameter of the developer tubing.

Abstract: Selective gas etching for self-aligned pattern transfer uses a first block and a separate second block formed in a sacrificial layer to transfer critical dimensions to a desired final layer using a selective gas etching process. The first block is a first hardmask material that can be plasma etched using a first gas, and the second block is a second hardmask material that can be plasma etched using a second gas separate from the first gas. The first hardmask material is not plasma etched using the second gas, and the second hardmask material is not plasma etched using the first gas.