Patents by Inventor Yoshihiro Izumi

Yoshihiro Izumi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20030227592
    Abstract: A wiring substrate is arranged so that a first periphery electric wiring and a second periphery electric wiring are patterned on an active matrix substrate, and a TCP as a electronic component is provided on a portion of the patterned electric wiring. The first periphery electric wiring and the second periphery electric wiring are formed by including a metal thin film and a transferred metal film. Further, in the portion where the TCP is provided, the first periphery electric wiring and the second periphery electric wiring either have a monolayer structure with one of the metal thin film and the transferred metal film, or have a lamination structure with both of the metal thin film and the transferred metal film. On this account, connection failure can be prevented on a low resistance wiring substrate.
    Type: Application
    Filed: June 5, 2003
    Publication date: December 11, 2003
    Inventors: Yoshihiro Izumi, Toshihiko Nakagawa
  • Publication number: 20030214475
    Abstract: A display medium includes a sheet having a first main surface and a second main surface opposite to each other, a first area where information is statically displayed, and a second area where information is dynamically displayed. A static display medium is located in the first area of the sheet and a dynamic display medium is located in the second area of the sheet. The static display medium and the dynamic display medium are integrated in the sheet and form a portion of the sheet, and are preferably substantially flush with one of the first main surface and the second main surface of the sheet. The static display medium and the dynamic display medium share at least one common element including one of a conductive ink, a black matrix and a color filter.
    Type: Application
    Filed: May 14, 2003
    Publication date: November 20, 2003
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Yoshihiro Izumi, Masahiro Shimizu
  • Patent number: 6649438
    Abstract: A TFT array is formed on a glass substrate (step P1). A surface protection layer is formed on the glass substrate so as to cover the TFT array (step P2). The glass substrate is divided to form active matrix, substrates with the surface protection layer being provided (step P3). The divided active matrix substrate is chamfered along its edges (step P4). The surface protection layer is removed from the active matrix substrate (step P5). An X-ray conductive layer is formed on the TFT array where the surface protection layer has been removed (step P6). By these steps, pollutants produced during the division and chamfering of the glass substrate are prevented from polluting the TFT array and the X-ray conductive layer, and the active element array and the semiconductor layer is prevented from deteriorating in terms of performance in manufacturing process for a two-dimensional image detector.
    Type: Grant
    Filed: December 27, 2002
    Date of Patent: November 18, 2003
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yoshihiro Izumi, Osamu Teranuma, Toshinori Yoshimuta, Shinya Hirasawa
  • Publication number: 20030209736
    Abstract: On a transparent electrically insulating substrate, formed are a scanning line, and a gate electrode of a switching element, further formed are a gate insulating film, a semiconductor layer, an n+-Si layer to be formed into a source electrode and a drain electrode. After the patterning of the foregoing structure, the dielectric film is formed, and the portion corresponding to the contact hole is removed by etching, and photosensitive resin is applied to form the interlayer insulating film. Then, the transparent electrode is extended from the pixel electrode over the switching element, whereon a conversion layer and a gold layer for use in electrode are vapor-deposited. In this structure, an increase in capacitor between the pixel electrode and the signal line can be suppressed by the interlayer insulating film, and the transparent electrode functions as a top gate and release excessive electric charge.
    Type: Application
    Filed: June 11, 2003
    Publication date: November 13, 2003
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Hisashi Nagata, Yoshihiro Izumi
  • Patent number: 6646266
    Abstract: In the present invention, the thickness of an insulating resin 6, in an area Y1 of an active matrix substrate 2 on which a semiconductor film 3 is formed, is equal to the thickness in an area X1 of the active matrix substrate 2 on which the semiconductor film 3 is not formed. On this account, in a flat panel image sensor 1, stress generated inside the insulating resin 6 is reduced, warpage of the active matrix substrate 2 is prevented in advance, and impact resistance of the flat panel image sensor 1 is improved.
    Type: Grant
    Filed: December 20, 2001
    Date of Patent: November 11, 2003
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Yoshihiro Izumi
  • Publication number: 20030207567
    Abstract: A SnO2 film having a prescribed pattern feature is formed on a substrate by a wet film-formation technology (e.g., sol-gel method). A Ni film is formed on the SnO2 film by an electroless plating method. The electroless plating method is conducted in the presence of at least one sulfur-containing compound selected from the group consisting of thiosulfates, thiocyanates and sulfur-containing organic compounds.
    Type: Application
    Filed: June 5, 2003
    Publication date: November 6, 2003
    Applicants: Sharp Kabushiki Kaisha, Meltex, Inc., Sumitomo Osaka Cemento Co., Ltd.
    Inventors: Yoshihiro Izumi, Yoshimasa Chikama, Satoshi Kawashima, Takaharu Hashimoto, Itsuji Yoshikawa, Masaaki Ishikawa
  • Patent number: 6642541
    Abstract: On a transparent electrically insulating substrate, formed are a scanning line, and a gate electrode of a switching element, further formed are a gate insulating film, a semiconductor layer, an n+-Si layer to be formed into a source electrode and a drain electrode. After the patterning of the foregoing structure, the dielectric film is formed, and the portion corresponding to the contact hole is removed by etching, and photosensitive resin is applied to form the interlayer insulating film. Then, the transparent electrode is extended from the pixel electrode over the switching element, whereon a conversion layer and a gold layer for use in electrode are vapor-deposited. In this structure, an increase in capacitor between the pixel electrode and the signal line can be suppressed by the interlayer insulating film, and the transparent electrode functions as a top gate and release excessive electric charge.
    Type: Grant
    Filed: March 2, 2001
    Date of Patent: November 4, 2003
    Assignee: Sharp Kabushikikaisha
    Inventors: Hisashi Nagata, Yoshihiro Izumi
  • Patent number: 6638782
    Abstract: A TFT array is formed on a glass substrate (step P1) A surface protection layer is formed on the glass substrate so as to cover the TFT a-ray (step P2). The glass substrate is divided to form active matrix substrates with the surface protection layer being provided (step P3). The divided active matrix substrate is chamfered along its edges (step P4). The surface protection layer is removed from the active matrix substrate (step P5). An X-ray conductive layer is formed on the TFT array where the surface protection layer has been removed (step P6). By these steps, pollutants produced during the division and chamfering of the glass substrate are prevented from polluting the TFT array and the X-ray conductive layer, and the active element array and the semiconductor layer is prevented from deteriorating in terms of performance in manufacturing process for a two-dimensional image detector.
    Type: Grant
    Filed: December 27, 2002
    Date of Patent: October 28, 2003
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yoshihiro Izumi, Osamu Teranuma, Toshinori Yoshimuta, Shinya Hirasawa
  • Patent number: 6627544
    Abstract: A SnO2 film having a prescribed pattern feature is formed on a substrate by a wet film-formation technology (e.g., sol-gel method). A Ni film is formed on the SnO2 film by an electroless plating method. The electroless plating method is conducted in the presence of at least one sulfur-containing compound selected from the group consisting of thiosulfates, thiocyanates and sulfur-containing organic compounds.
    Type: Grant
    Filed: May 22, 2002
    Date of Patent: September 30, 2003
    Assignees: Sharp Kabushiki Kaisha, Meltex Inc., Sumitomo Osaka Cemento Co., Ltd.
    Inventors: Yoshihiro Izumi, Yoshimasa Chikama, Satoshi Kawashima, Takaharu Hashimoto, Itsuji Yoshikawa, Masaaki Ishikawa
  • Publication number: 20030179169
    Abstract: An electronic appliance includes an array of elements and an addressing substrate. The array of elements includes: first and second surfaces opposed to each other; element regions, arranged in matrix between the first and second surfaces and including electrodes; and a first group of terminal electrodes on the second surface, each of which is electrically connected to associated one of the electrodes. The addressing substrate includes: a substrate having a third surface opposed to the second surface; a second group of terminal electrodes on the third surface, each of which is electrically connected to associated one of the terminal electrodes in the first group; and an addressing driver, which transmits or receives a predetermined signal to/from the element regions via the second group of terminal electrodes while addressing the element regions one after another.
    Type: Application
    Filed: March 13, 2003
    Publication date: September 25, 2003
    Inventor: Yoshihiro Izumi
  • Patent number: 6603106
    Abstract: The invention provides a two-dimensional image detector having superior uniformity in thickness and composition of a photoconductive layer with respect to the entire substrate, and a method of productively (efficiently) and inexpensively manufacturing such a two-dimensional image detector. The two-dimensional image detector includes at least an active matrix substrate 1 having a plurality of pixel electrodes 10, and a photoconductive layer 2 stacked on the pixel electrodes 10, wherein the photoconductive layer 2 is transferred to the active matrix substrate 1 after being formed in a predetermined thickness on a transfer substrate. That is, a fabrication method of the two-dimensional image detector is the method in which the photoconductive layer 2 is formed in advance in a predetermined thickness on the transfer substrate and then transferred on the active matrix substrate 1. The photoconductive layer 2 includes a mixture of particulate photoconductors and a binder.
    Type: Grant
    Filed: January 23, 2001
    Date of Patent: August 5, 2003
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Osamu Teranuma, Yoshihiro Izumi
  • Publication number: 20030137794
    Abstract: A display device includes a display panel and an ion generator for generating positive ions and negative ions. The display device kills microorganisms or decomposes and removes harmful organic substances (e.g., sources of odor or environmental hormones), which exist either on the screen or in the air surrounding the display device, by utilizing the action of the positive and negative ions.
    Type: Application
    Filed: January 23, 2003
    Publication date: July 24, 2003
    Inventors: Yoshihiro Izumi, Yasukuni Yamane
  • Patent number: 6593577
    Abstract: An electromagnetic wave detecting device is provided with an active matrix substrate having signal input terminals and signal output terminals in its circumference, a semiconductor film, provided on the active matrix substrate, having electromagnetic wave conductivity, and a bias electrode having a connecting section, to which a bias supply power source is connected, for applying a bias voltage to the semiconductor film, and at least one of the signal input terminals and the signal output terminals are provided offset so as to be on a side which is away from the connecting section of the bias electrode, which makes it possible to prevent an unnecessary electric discharge between the connecting section of the bias electrode and at least one of the signal input terminals and the signal output terminals.
    Type: Grant
    Filed: January 3, 2002
    Date of Patent: July 15, 2003
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Yoshihiro Izumi
  • Publication number: 20030102424
    Abstract: An active-matrix substrate is provided with electrode wires disposed in a lattice form, a plurality of switching elements disposed respectively at intersections of the electrode wires, and connecting terminals for connecting the electrode wires to the outside, the electrode wires include metal electrodes, and at least parts of the connecting terminals have a property of transmitting light. A two-dimensional image detector includes the active-matrix substrate and the amorphous semiconductor layer, which is formed on the active-matrix substrate and has electromagnetic wave conductivity. The connecting terminals are connected with the outside via an anisotropic conductive adhesive having photo-reactivity. A display device includes the active-matrix substrate and an opposing substrate which is disposed so as to oppose the active-matrix substrate via an electro-optical medium, and the connecting terminals are connected to the outside via an anisotropic conductive adhesive having photo-reactivity.
    Type: Application
    Filed: October 7, 2002
    Publication date: June 5, 2003
    Applicant: Sharp Kabushiki Kaisha.
    Inventors: Yoshihiro Izumi, Osamu Teranuma
  • Publication number: 20030100138
    Abstract: A TFT array is formed on a glass substrate (step P1) A surface protection layer is formed on the glass substrate so as to cover the TFT a-ray (step P2). The glass substrate is divided to form active matrix substrates with the surface protection layer being provided (step P3). The divided active matrix substrate is chamfered along its edges (step P4). The surface protection layer is removed from the active matrix substrate (step P5). An X-ray conductive layer is formed on the TFT array where the surface protection layer has been removed (step P6). By these steps, pollutants produced during the division and chamfering of the glass substrate are prevented from polluting the TFT array and the X-ray conductive layer, and the active element array and the semiconductor layer is prevented from deteriorating in terms of performance in manufacturing process for a two-dimensional image detector.
    Type: Application
    Filed: December 27, 2002
    Publication date: May 29, 2003
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Yoshihiro Izumi, Osamu Teranuma, Toshinori Yoshimuta, Shinya Hirasawa
  • Publication number: 20030096445
    Abstract: A TFT array is formed on a glass substrate (step P1). A surface protection layer is formed on the glass substrate so as to cover the TFT array (step P2). The glass substrate is divided to form active matrix substrates with the surface protection layer being provided (step P3). The divided active matrix substrate is chamfered along its edges (step P4). The surface protection layer is removed from the active matrix substrate (step P5). An X-ray conductive layer is formed on the TFT array where the surface protection layer has been removed (step P6). By these steps, pollutants produced during the division and chamfering of the glass substrate are prevented from polluting the TFT array and the X-ray conductive layer, and the active element array and the semiconductor layer is prevented from deteriorating in terms of performance in manufacturing process for a two-dimensional image detector.
    Type: Application
    Filed: December 27, 2002
    Publication date: May 22, 2003
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Yoshihiro Izumi, Osamu Teranuma, Toshinori Yoshimuta, Shinya Hirasawa
  • Patent number: 6564744
    Abstract: The present invention provides a plasma CVD method for forming a plasma from a deposition material gas by application of an electric power, and thereby forming a film on a deposition target object in the plasma, wherein the formation of the plasma from the material gas is performed by applying an RF power and a DC power, and the DC power is applied to an electrode carrying the deposition target object. The present invention also provides a plasma CVD apparatus for forming a plasma from a deposition material gas by applying an electric power from the power applying means, and thereby forming a film on a deposition target object by exposing the deposition target object to the plasma, wherein the power applying means includes RF power applying means and DC power applying means, and the DC power applying means applies an electric power to the electrode carrying the deposition target object.
    Type: Grant
    Filed: October 18, 2001
    Date of Patent: May 20, 2003
    Assignee: Nissin Electric Co., Ltd.
    Inventors: Takahiro Nakahigashi, Akira Doi, Yoshihiro Izumi, Hajime Kuwahara
  • Patent number: 6562659
    Abstract: When TCP substrates serving as external circuits are packaged by thermocompression bonding onto input/output terminals on an active-matrix substrate including an a-Se film serving as an amorphous semiconductor layer, a cooling operation is performed by a cooling medium discharging nozzle on at least a part between the a-Se film and a thermocompression bonding part disposed between the TCP substrates and the input/output terminals on the active-matrix substrate. Thus, during the thermocompression bonding, a temperature of the a-Se film is maintained below its crystallizing temperature so as to prevent exfoliation of the amorphous semiconductor film and deterioration in characteristics thereof, upon packaging the external circuits by thermocompression bonding onto the input/output terminals on the substrate including the amorphous semiconductor film.
    Type: Grant
    Filed: June 2, 2000
    Date of Patent: May 13, 2003
    Assignees: Sharp Kabushiki Kaisha, Shimadzu Corporation
    Inventors: Yoshihiro Izumi, Osamu Teranuma
  • Patent number: 6559451
    Abstract: A TFT array is formed on a glass substrate (step P1). A surface protection layer is formed on the glass substrate so as to cover the TFT array (step P2). The glass substrate is divided to form active matrix substrates with the surface protection layer being provided (step P3). The divided active matrix substrate is chamfered along its edges (step P4). The surface protection layer is removed from the active matrix substrate (step P5). An X-ray conductive layer is formed on the TFT array where the surface protection layer has been removed (step P6). By these steps, pollutants produced during the division and chamfering of the glass substrate are prevented from polluting the TFT array and the X-ray conductive layer, and the active element array and the semiconductor layer is prevented from deteriorating in terms of performance in manufacturing process for a two-dimensional image detector.
    Type: Grant
    Filed: September 8, 2000
    Date of Patent: May 6, 2003
    Assignees: Sharp Kabushiki Kaisha, Shimadzu Corporation
    Inventors: Yoshihiro Izumi, Osamu Teranuma, Toshinori Yoshimuta, Shinya Hirasawa
  • Publication number: 20030038306
    Abstract: In an active matrix substrate, a glass substrate is provided with TFTs having gate electrodes connected to scanning lines also provided on the glass substrate. The glass substrate is further provided with auxiliary capacitance lines, formed on the same layer as the scanning lines. Further, pixel electrodes connected to drain electrodes of the TFTs are formed on the same layer as signal lines connected to source electrodes of the TFTs. An insulating layer is provided between the layer forming the signal lines and pixel electrodes and the layer forming the drain and source electrodes. Since the insulating film is present between the signal lines and the scanning and auxiliary capacitance lines, influence on the auxiliary capacitance value can be reduced, as can a signal line capacitance value. As a result, even when the auxiliary capacitance value is increased, the signal line capacitance value remains small.
    Type: Application
    Filed: August 27, 2002
    Publication date: February 27, 2003
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Yoshihiro Izumi, Hisashi Nagata, Yuichi Saito