Patents by Inventor Yoshihiro Uozumi

Yoshihiro Uozumi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11921428
    Abstract: According to one embodiment, a substrate processing method is disclosed. The method can include treating a substrate with a first liquid. The substrate has a structural body formed on a major surface of the substrate. The method can include forming a support member supporting the structural body by bringing a second liquid into contact with the substrate wetted by the first liquid, and changing at least a portion of the second liquid into a solid by carrying out at least one of causing the second liquid to react, reducing a quantity of a solvent included in the second liquid, and causing at least a portion of a substance dissolved in the second liquid to be separated. The method can include removing the support member by changing at least a part of the support member from a solid phase to a gaseous phase, without passing through a liquid phase.
    Type: Grant
    Filed: February 25, 2022
    Date of Patent: March 5, 2024
    Assignee: Kioxia Corporation
    Inventors: Yoshihiro Uozumi, Shinsuke Kimura, Yoshihiro Ogawa, Hiroyasu Iimori, Tatsuhiko Koide, Hideaki Hirabayashi, Yuji Nagashima
  • Publication number: 20230130044
    Abstract: A method for manufacturing a semiconductor device is provided, including: preparing a first chip forming portion having a first semiconductor substrate, first metal pads provided at the substrate and a first circuit electrically connected to at least a part of the pads, and a second chip forming portion having a second semiconductor substrate, second metal pads provided at substrate and a second circuit electrically connected to at least a part of the pads; bonding the first and the second chip forming portions while joining the first and the second pads to form a bonding substrate having a non-bonded region between the first and the second chip forming portions at an outer peripheral portion thereof; and filling an insulating film into the non-bonded region, at least a part of the insulating film containing at least one selected from the group consisting of silicon nitride and nitrogen-containing silicon carbide.
    Type: Application
    Filed: December 23, 2022
    Publication date: April 27, 2023
    Applicant: Kioxia Corporation
    Inventor: Yoshihiro UOZUMI
  • Patent number: 11621239
    Abstract: A semiconductor device according to an embodiment includes: a bonding substrate which includes a first chip forming portion having first metal pads provided at a semiconductor substrate and a first circuit connected to the first metal pads, and a second chip forming portion having second metal pads joined to the first metal pads and a second circuit connected to the second metal pads and being bonded to the first chip forming portion; and an insulating film which is filled into a non-bonded region between the first chip forming portion and the second chip forming portion at an outer peripheral portion of the bonding substrate. At least a part of the insulating film contains at least one selected from the group consisting of silicon nitride and nitrogen-containing silicon carbide.
    Type: Grant
    Filed: September 14, 2020
    Date of Patent: April 4, 2023
    Assignee: Kioxia Corporation
    Inventor: Yoshihiro Uozumi
  • Patent number: 11581277
    Abstract: A semiconductor device according to an embodiment includes: a bonding substrate which includes a first chip forming portion having first metal pads provided at a semiconductor substrate and a first circuit connected to the first metal pads, and a second chip forming portion having second metal pads joined to the first metal pads and a second circuit connected to the second metal pads and being bonded to the first chip forming portion; and an insulating film which is filled into a non-bonded region between the first chip forming portion and the second chip forming portion at an outer peripheral portion of the bonding substrate. At least a part of the insulating film contains at least one selected from the group consisting of silicon nitride and nitrogen-containing silicon carbide.
    Type: Grant
    Filed: September 14, 2020
    Date of Patent: February 14, 2023
    Assignee: Kioxia Corporation
    Inventor: Yoshihiro Uozumi
  • Publication number: 20220181171
    Abstract: According to one embodiment, a substrate processing method is disclosed. The method can include treating a substrate with a first liquid. The substrate has a structural body formed on a major surface of the substrate. The method can include forming a support member supporting the structural body by bringing a second liquid into contact with the substrate wetted by the first liquid, and changing at least a portion of the second liquid into a solid by carrying out at least one of causing the second liquid to react, reducing a quantity of a solvent included in the second liquid, and causing at least a portion of a substance dissolved in the second liquid to be separated. The method can include removing the support member by changing at least a part of the support member from a solid phase to a gaseous phase, without passing through a liquid phase.
    Type: Application
    Filed: February 25, 2022
    Publication date: June 9, 2022
    Applicant: KIOXIA CORPORATION
    Inventors: Yoshihiro UOZUMI, Shinsuke KIMURA, Yoshihiro OGAWA, Hiroyasu IIMORI, Tatsuhiko KOIDE, Hideaki HIRABAYASHI, Yuji NAGASHIMA
  • Publication number: 20210091024
    Abstract: A semiconductor device according to an embodiment includes: a bonding substrate which includes a first chip forming portion having first metal pads provided at a semiconductor substrate and a first circuit connected to the first metal pads, and a second chip forming portion having second metal pads joined to the first metal pads and a second circuit connected to the second metal pads and being bonded to the first chip forming portion; and an insulating film which is filled into a non-bonded region between the first chip forming portion and the second chip forming portion at an outer peripheral portion of the bonding substrate. At least a part of the insulating film contains at least one selected from the group consisting of silicon nitride and nitrogen-containing silicon carbide.
    Type: Application
    Filed: September 14, 2020
    Publication date: March 25, 2021
    Applicant: Kioxia Corporation
    Inventor: Yoshihiro UOZUMI
  • Publication number: 20190214277
    Abstract: According to one embodiment, a substrate processing method is disclosed. The method can include treating a substrate with a first liquid. The substrate has a structural body formed on a major surface of the substrate. The method can include forming a support member supporting the structural body by bringing a second liquid into contact with the substrate wetted by the first liquid, and changing at least a portion of the second liquid into a solid by carrying out at least one of causing the second liquid to react, reducing a quantity of a solvent included in the second liquid, and causing at least a portion of a substance dissolved in the second liquid to be separated. The method can include removing the support member by changing at least a part of the support member from a solid phase to a gaseous phase, without passing through a liquid phase.
    Type: Application
    Filed: March 18, 2019
    Publication date: July 11, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Yoshihiro Uozumi, Shinsuke Kimura, Yoshihiro Ogawa, Hiroyasu Iimori, Tatsuhiko Koide, Hideaki Hirabayashi, Yuji Nagashima
  • Patent number: 9929017
    Abstract: An etching method according to an embodiment, includes performing etching on a material having tungsten (W) as a main component by using as an etchant a chemical solution having hydrogen peroxide as a main component. The chemical solution contains 12 ppm or more and 100,000 ppm or less of W.
    Type: Grant
    Filed: March 7, 2013
    Date of Patent: March 27, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Nagisa Takami, Yoshihiro Uozumi
  • Patent number: 9553189
    Abstract: According to certain embodiments, a silicide layer is formed after the fabrication of a functional gate electrode using a gate-last scheme. An initial semiconductor structure has at least one impurity regions formed on a semiconductor substrate, a sacrifice film formed over the impurity region, an isolation layer formed over the sacrifice film and a dielectric layer formed over the isolation film. A via is patterned into the dielectric layer of the initial semiconductor structure and through the thickness of the isolation layer such that a contact opening is formed in the isolation layer. The sacrifice film underlying the isolation layer is then removed leaving a void space underlying the isolation layer. Then, a metal silicide precursor is placed within the void space, and the metal silicide precursor is converted to a silicide layer through an annealing process.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: January 24, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yoshihiro Uozumi
  • Publication number: 20160071747
    Abstract: According to one embodiment, a substrate processing method is disclosed. The method can include treating a substrate with a first liquid. The substrate has a structural body formed on a major surface of the substrate. The method can include forming a support member supporting the structural body by bringing a second liquid into contact with the substrate wetted by the first liquid, and changing at least a portion of the second liquid into a solid by carrying out at least one of causing the second liquid to react, reducing a quantity of a solvent included in the second liquid, and causing at least a portion of a substance dissolved in the second liquid to be separated. The method can include removing the support member by changing at least a part of the support member from a solid phase to a gaseous phase, without passing through a liquid phase.
    Type: Application
    Filed: November 13, 2015
    Publication date: March 10, 2016
    Inventors: Yoshihiro Uozumi, Shinsuke Kimura, Yoshihiro Ogawa, Hiroyasu limori, Tatsuhiko Koide, Hideaki Hirabayashi, Yuji Nagashima
  • Patent number: 9213242
    Abstract: According to one embodiment, a substrate processing method is disclosed. The method can include treating a substrate with a first liquid. The substrate has a structural body formed on a major surface of the substrate. The method can include forming a support member supporting the structural body by bringing a second liquid into contact with the substrate wetted by the first liquid, and changing at least a portion of the second liquid into a solid by carrying out at least one of causing the second liquid to react, reducing a quantity of a solvent included in the second liquid, and causing at least a portion of a substance dissolved in the second liquid to be separated. The method can include removing the support member by changing at least a part of the support member from a solid phase to a gaseous phase, without passing through a liquid phase.
    Type: Grant
    Filed: July 3, 2012
    Date of Patent: December 15, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshihiro Uozumi, Shinsuke Kimura, Yoshihiro Ogawa, Hiroyasu Iimori, Tatsuhiko Koide, Hideaki Hirabayashi, Yuji Nagashima
  • Publication number: 20150318395
    Abstract: According to certain embodiments, a silicide layer is formed after the fabrication of a functional gate electrode using a gate-last scheme. An initial semiconductor structure has at least one impurity regions formed on a semiconductor substrate, a sacrifice film formed over the impurity region, an isolation layer formed over the sacrifice film and a dielectric layer formed over the isolation film. A via is patterned into the dielectric layer of the initial semiconductor structure and through the thickness of the isolation layer such that a contact opening is formed in the isolation layer. The sacrifice film underlying the isolation layer is then removed leaving a void space underlying the isolation layer. Then, a metal silicide precursor is placed within the void space, and the metal silicide precursor is converted to a silicide layer through an annealing process.
    Type: Application
    Filed: June 29, 2015
    Publication date: November 5, 2015
    Inventor: Yoshihiro Uozumi
  • Patent number: 9099474
    Abstract: According to certain embodiments, a silicide layer is formed after the fabrication of a functional gate electrode using a gate-last scheme. An initial semiconductor structure has at least one impurity regions formed on a semiconductor substrate, a sacrifice film formed over the impurity region, an isolation layer formed over the sacrifice film and a dielectric layer formed over the isolation film. A via is patterned into the dielectric layer of the initial semiconductor structure and through the thickness of the isolation layer such that a contact opening is formed in the isolation layer. The sacrifice film underlying the isolation layer is then removed leaving a void space underlying the isolation layer. Then, a metal silicide precursor is placed within the void space, and the metal silicide precursor is converted to a silicide layer through an annealing process.
    Type: Grant
    Filed: December 6, 2012
    Date of Patent: August 4, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yoshihiro Uozumi
  • Patent number: 8946809
    Abstract: According to one embodiment, a method is disclosed for manufacturing a semiconductor memory device. The method includes forming a first stopper film forming a lower gate layer, making a recess in the lower gate layer, filling a sacrificial film into the recess, forming a second stopper film, making an opening in the second stopper film, forming a stacked body. The stacked body includes electrode films and insulating films. The method includes, making a slit in the stacked body, making a hole in the stacked body, removing the sacrificial film via the hole, forming a memory film including a charge storage film. The method includes forming a channel body on a side wall of the memory film. An etching rate of the first stopper film and the second stopper film is lower than an etching rate of the electrode films and the insulating films.
    Type: Grant
    Filed: September 4, 2013
    Date of Patent: February 3, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuhide Takamura, Ryota Katsumata, Masaru Kidoh, Yoshihiro Uozumi, Daigo Ichinose, Toru Matsuda
  • Patent number: 8912089
    Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes forming a stacked body on a substrate. The stacked body includes a plurality of first conductive layers including a metallic element as a main component and a plurality of second conductive layers including a metallic element as a main component provided respectively between the first conductive layers. The method includes making a hole to pierce the stacked body. The method includes making a slit to divide the stacked body. The method includes making a gap between the first conductive layers by removing the second conductive layers by etching via the slit or the hole. The method includes forming a memory film including a charge storage film at a side wall of the hole. The method includes forming a channel body on an inner side of the memory film inside the hole.
    Type: Grant
    Filed: March 21, 2013
    Date of Patent: December 16, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Seiichi Omoto, Yoshihiro Uozumi, Tadashi Iguchi, Osamu Yamane, Kazuyuki Masukawa, Yoshihiro Yanai
  • Publication number: 20140284691
    Abstract: According to one embodiment, a method is disclosed for manufacturing a semiconductor memory device. The method includes forming a first stopper film forming a lower gate layer, making a recess in the lower gate layer, filling a sacrificial film into the recess, forming a second stopper film, making an opening in the second stopper film, forming a stacked body. The stacked body includes electrode films and insulating films. The method includes, making a slit in the stacked body, making a hole in the stacked body, removing the sacrificial film via the hole, forming a memory film including a charge storage film. The method includes forming a channel body on a side wall of the memory film. An etching rate of the first stopper film and the second stopper film is lower than an etching rate of the electrode films and the insulating films.
    Type: Application
    Filed: September 4, 2013
    Publication date: September 25, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kazuhide Takamura, Ryota Katsumata, Masaru Kidoh, Yoshihiro Uozumi, Daigo Ichinose, Toru Matsuda
  • Publication number: 20140073069
    Abstract: An etching method according to an embodiment, includes performing etching on a material having tungsten (W) as a main component by using as an etchant a chemical solution having hydrogen peroxide as a main component. The chemical solution contains 12 ppm or more and 100,000 ppm or less of W.
    Type: Application
    Filed: March 7, 2013
    Publication date: March 13, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Nagisa TAKAMI, Yoshihiro UOZUMI
  • Publication number: 20140061752
    Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes forming a stacked body on a substrate. The stacked body includes a plurality of first conductive layers including a metallic element as a main component and a plurality of second conductive layers including a metallic element as a main component provided respectively between the first conductive layers. The method includes making a hole to pierce the stacked body. The method includes making a slit to divide the stacked body. The method includes making a gap between the first conductive layers by removing the second conductive layers by etching via the slit or the hole. The method includes forming a memory film including a charge storage film at a side wall of the hole. The method includes forming a channel body on an inner side of the memory film inside the hole.
    Type: Application
    Filed: March 21, 2013
    Publication date: March 6, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Seiichi Omoto, Yoshihiro Uozumi, Tadashi Iguchi, Osamu Yamane, Kazuyuki Masukawa, Yoshihiro Yanai
  • Patent number: 8513140
    Abstract: A post-dry etching cleaning liquid composition for cleaning a substrate after dry etching is provided, the cleaning liquid composition containing at least one type of fluorine compound, glyoxylic acid, at least one type of organic acid salt, and water. With regard to the fluorine compound, ammonium fluoride may be used. With regard to the organic acid salt, at least one of ammonium oxalate, ammonium tartarate, ammonium citrate, and ammonium acetate may be used.
    Type: Grant
    Filed: September 23, 2010
    Date of Patent: August 20, 2013
    Assignees: Sony Corporation, Kabushiki Kaisha Toshiba, Kanto Kagaku Kabushiki Kaisha
    Inventors: Masafumi Muramatsu, Kazumi Asada, Yukino Hagino, Atsushi Okuyama, Takahito Nakajima, Kazuhiko Takase, Yoshihiro Uozumi, Tsuyoshi Matsumura, Takuo Ohwada, Norio Ishikawa
  • Publication number: 20130196512
    Abstract: According to one embodiment, a method is disclosed for manufacturing a semiconductor device. The method can rinse a substrate with water, a plurality of protruding patterns being formed on the substrate. The method can dry the substrate by removing water from a recess between the protruding patterns by irradiating microwaves.
    Type: Application
    Filed: August 27, 2012
    Publication date: August 1, 2013
    Inventors: Tatsuhiko KOIDE, Yoshihiro OGAWA, Yoshihiro UOZUMI