Patents by Inventor Yoshihisa Nagano

Yoshihisa Nagano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6326671
    Abstract: A semiconductor memory device, includes: a semiconductor substrate including a transistor; a first protective insulating film for covering the semiconductor substrate; at least one data storage capacitor element formed on the first protective insulating film; a second protective insulating film for covering the first protective insulating film and the capacitor element; a hydrogen carrier layer; and an interconnection layer for electrically connecting the transistor and the capacitor element, wherein: the capacitor element includes a lower electrode formed on the first protective insulating film, a capacitor film formed on the lower electrode, and an upper electrode formed on the capacitor film, the capacitor film includes an insulating metal oxide, the second protective insulating film has a first contact hole reaching the upper electrode and a second contact hole reaching the lower electrode, and the hydrogen barrier layer is provided in the first and second contact holes, so as not to expose the upper and
    Type: Grant
    Filed: December 1, 1999
    Date of Patent: December 4, 2001
    Assignee: Matsushita Electronics Corporation
    Inventors: Yoshihisa Nagano, Keisuke Tanaka, Toru Nasu
  • Patent number: 6320214
    Abstract: The present invention provides a semiconductor device including a semiconductor element and a dummy semiconductor element adjacent to the semiconductor element. When the semiconductor element is a capacitor element including a bottom electrode, a top electrode and a dielectric layer between the electrodes, a dummy capacitor element also has dummy electrodes and a dummy dielectric layer between the dummy electrodes. The dummy electrode is located so that a space between the top electrode of the capacitor element ad the dummy top electrode is in a predetermined range (e.g. 0.3 &mgr;m to 14 &mgr;m). The dummy capacitor element prevents the capacitor dielectric layer from degrading since the collision of the etching ions with the capacitor dielectric layer in a dry etching process is suppressed.
    Type: Grant
    Filed: December 11, 1998
    Date of Patent: November 20, 2001
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Akihiro Matsuda, Yoshihisa Nagano, Yasuhiro Uemoto
  • Publication number: 20010028074
    Abstract: A capacitor including a capacitor lower electrode, a capacitor dielectric film of a highly dielectric film or a ferroelectric film and a capacitor upper electrode is formed on a semiconductor substrate. A protection film is formed on the semiconductor substrate so as to cover the capacitor. A first TEOS film having a relatively large water content is formed on the protection film through first TEOS-O3 CVD where an ozone concentration is relatively low. A second TEOS-O3 film having a relatively small water content is formed on the first TEOS-O3 film through second TEOS-O3 CVD where the ozone concentration is relatively high.
    Type: Application
    Filed: February 9, 2001
    Publication date: October 11, 2001
    Inventors: Toshie Kutsunai, Shinichiro Hayashi, Yuji Judai, Yoshihisa Nagano
  • Patent number: 6294438
    Abstract: A semiconductor device forming a capacitor through an interlayer insulating layer on a semiconductor substrate on which an integrated circuit is formed. This semiconductor device has an interlayer insulating layer with moisture content of 0.5 g/cm3 or less, which covers the capacitor in one aspect, and has a passivation layer with hydrogen content of 1021 atoms/cm3 or less, which covers the interconnections of the capacitor in other aspect. By thus constituting, deterioration of the capacitor dielectric can be prevented which brings about the electrical reliability of the ferroelectric layer or high dielectric layer.
    Type: Grant
    Filed: June 8, 2000
    Date of Patent: September 25, 2001
    Assignee: Matsushita Electronics Corporation
    Inventors: Koji Arita, Eiji Fujii, Yasuhiro Shimada, Yasuhiro Uemoto, Toru Nasu, Akihiro Matsuda, Yoshihisa Nagano, Atsuo Inoue, Taketoshi Matsuura, Tatsuo Otsuki
  • Publication number: 20010020709
    Abstract: The semiconductor device of the invention includes a capacitor device, which is formed on a substrate and which includes a capacitive lower electrode, a capacitive insulating film made of an insulating metal oxide film and a capacitive upper electrode. An interlevel insulating film having an opening reaching the capacitive upper electrode is formed over the capacitor device. A metal interconnection including a titanium film is formed over the interlevel insulating film so as to be electrically connected to the capacitive upper electrode through the opening. An anti-diffusion film having conductivity is formed between the capacitive upper electrode and the metal interconnection for preventing titanium atoms composing the titanium film of the metal interconnection from passing through the capacitive upper electrode and diffusing into the capacitive insulating film.
    Type: Application
    Filed: March 5, 2001
    Publication date: September 13, 2001
    Applicant: Matsushita Electronics Corporation
    Inventors: Keisaku Nakao, Akihiro Matsuda, Yasufumi Izutsu, Toyoji Ito, Takumi Mikawa, Toru Nasu, Yoshihisa Nagano, Keisuke Tanaka, Toshie Kutsunai
  • Publication number: 20010019874
    Abstract: A method for fabricating a capacitor for an integrated circuit, comprising the steps of forming a titanium film for an adhesion layer over a substrate, forming a titanium dioxide film for a diffusion barrier layer by annealing the titanium film after ion-implantation of oxygen ion into a surface region of the titanium film so as to change titanium in the surface region to titanium dioxide, and forming a high dielectric constant capacitor on the titanium dioxide film.
    Type: Application
    Filed: January 24, 2001
    Publication date: September 6, 2001
    Applicant: Matsushita Electronics Corporation
    Inventors: Yasuhiro Uemoto, Eiji Fujii, Koji Arita, Yoshihisa Nagano, Yasuhiro Shimada, Masamichi Azuma, Atsuo Inoue, Yasufumi Izutsu
  • Publication number: 20010015451
    Abstract: A semiconductor memory device according to the present invention includes a memory cell capacitor for storing data thereon. The capacitor is made up of a first electrode connected to a contact plug, a second electrode and a capacitive insulating film interposed between the first and second electrodes. The first electrode includes a first barrier film in contact with the contact plug and a second barrier film, which is formed on the first barrier film and prevents the diffusion of oxygen. The second barrier film covers the upper and side faces of the first barrier film.
    Type: Application
    Filed: February 20, 2001
    Publication date: August 23, 2001
    Inventors: Yoshihisa Nagano, Tooru Nasu, Shinichiro Hayashi, Eiji Fujii
  • Patent number: 6239462
    Abstract: The semiconductor device of the invention includes a capacitor device, which is formed on a substrate and which includes a capacitive lower electrode, a capacitive insulating film made of an insulating metal oxide film and a capacitive upper electrode. An interlevel insulating film having an opening reaching the capacitive upper electrode is formed over the capacitor device. A metal interconnection including a titanium film is formed over the interlevel insulating film so as to be electrically connected to the capacitive upper electrode through the opening. An anti-diffusion film having conductivity is formed between the capacitive upper electrode and the metal interconnection for preventing titanium atoms composing the titanium film of the metal interconnection from passing through the capacitive upper electrode and diffusing into the capacitive insulating film.
    Type: Grant
    Filed: July 23, 1998
    Date of Patent: May 29, 2001
    Assignee: Matsushita Electronics Corporation
    Inventors: Keisaku Nakao, Akihiro Matsuda, Yasufumi Izutsu, Toyoji Ito, Takumi Mikawa, Toru Nasu, Yoshihisa Nagano, Keisuke Tanaka, Toshie Kutsunai
  • Patent number: 6232131
    Abstract: The method for manufacturing a semiconductor device of this invention comprises the steps: forming a first wiring layer on a semiconductor substrate on which a capacitor element with a capacitor dielectric film is formed, and the capacitor dielectric film is at least one film selected from the group consisting of a capacitor dielectric film with high dielectric constant and a ferroelectric film; conducting a first annealing to said semiconductor substrate; forming a second wiring layer on said first wiring layer; etching selectively the first wiring layer and the second wiring layer; and conducting a second annealing to the semiconductor substrate, so that the stress provided to the capacitor element can be reduced by annealing after forming each wiring layer, and thus, it can prevent the increase of leakage current and deterioration of dielectric breakdown voltage of the capacitor element having a capacitor dielectric film comprising a high capacitor dielectric film and a ferroelectric film.
    Type: Grant
    Filed: June 24, 1998
    Date of Patent: May 15, 2001
    Assignee: Matsushita Electronics Corporation
    Inventors: Yoshihisa Nagano, Eiji Fujii, Yasuhiro Uemoto
  • Patent number: 6214660
    Abstract: A method for fabricating a capacitor for an integrated circuit, comprising the steps of forming a titanium film for an adhesion layer over a substrate, forming a titanium dioxide film for a diffusion barrier layer by annealing the titanium film after ion-implantation of oxygen ion into a surface region of the titanium film so as to change titanium in the surface region to titanium dioxide, and forming a high dielectric constant capacitor on the titanium dioxide film.
    Type: Grant
    Filed: October 23, 1998
    Date of Patent: April 10, 2001
    Assignee: Matsushita Electronics Corporation
    Inventors: Yasuhiro Uemoto, Eigi Fujii, Koji Arita, Yoshihisa Nagano, Yasuhiro Shimada, Masamichi Azuma, Atsuo Inoue, Yasufumi Izutsu
  • Patent number: 6204111
    Abstract: A method for fabricating a capacitor for an integrated circuit, comprising the steps of forming a titanium film for an adhesion layer over a substrate, forming a titanium dioxide film for a diffusion barrier layer by annealing the titanium film after ion-implantation of oxygen ion into a surface region of the titanium film so as to change titanium in the surface region to titanium dioxide, and forming a high dielectric constant capacitor on the titanium dioxide film.
    Type: Grant
    Filed: January 28, 1999
    Date of Patent: March 20, 2001
    Assignee: Matsushita Electronics Corporation
    Inventors: Yasuhiro Uemoto, Eiji Fujii, Koji Arita, Yoshihisa Nagano, Yasuhiro Shimada, Masamichi Azuma, Atsuo Inoue, Yasufumi Izutsu
  • Patent number: 6174822
    Abstract: A semiconductor device includes: a capacitor provided on a supporting substrate having an integrated circuit thereon and including a lower electrode, a dielectric film, and an upper electrode; a first interlayer insulating film provided so as to cover the capacitor; a first interconnect selectively provided on the first interlayer insulating film and electrically connected to the integrated circuit and the capacitor through a first contact hole formed in the first interlayer insulating film; a second interlayer insulating film formed of ozone TEOS and provided so as to cover the first interconnect; a second interconnect selectively provided on the second interlayer insulating film and electrically connected to the first interconnect through a second contact hole formed in the second interlayer insulating film; and a passivation layer provided so as to cover the second interconnect.
    Type: Grant
    Filed: October 20, 1998
    Date of Patent: January 16, 2001
    Assignee: Matsushita Electronics Corporation
    Inventors: Yoshihisa Nagano, Toshie Kutsunai, Yuji Judai, Yasuhiro Uemoto, Eiji Fujii
  • Patent number: 6169304
    Abstract: A semiconductor device forming a capacitor through an interlayer insulating layer on a semiconductor substrate on which an integrated circuit is formed. This semiconductor device has an interlayer insulating layer with moisture content of 0.5 g/cm3 or less, which covers the capacitor in one aspect, and has a passivation layer with hydrogen content of 1021 atoms/cm3 or less, which covers the interconnections of the capacitor in other aspect. By thus constituting, deterioration of the capacitor dielectric can be prevented which brings about the electrical reliability of the ferroelectric layer or high dielectric layer.
    Type: Grant
    Filed: May 4, 1998
    Date of Patent: January 2, 2001
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Koji Arita, Eiji Fujii, Yasuhiro Shimada, Yasuhiro Uemoto, Toru Nasu, Akihiro Matsuda, Yoshihisa Nagano, Atsuo Inoue, Taketoshi Matsuura, Tatsuo Otsuki
  • Patent number: 6166424
    Abstract: On a substrate, there are provided a lower electrode, a capacitance insulating film, a passivation insulating film, and a first partial film of an upper electrode to be filled in a second aperture (capacitance determining aperture) formed in the passivation insulating film. The lower electrode, the capacitance insulating film, and the first partial film constitute a capacitance element. The upper electrode has the first partial film which is in contact with the capacitance insulating film and a second partial film which is not in contact with the capacitance insulating film. Since a second electrode wire consisting of a lower-layer film composed of titanium and an upper-layer film composed of an aluminum alloy film is in contact with the second partial film distinct from the first partial film of the upper electrode, titanium or the like encroaching from the second electrode wire can be prevented from diffusing into the capacitance insulating film.
    Type: Grant
    Filed: July 2, 1998
    Date of Patent: December 26, 2000
    Assignee: Matsushita Electronics Corporation
    Inventors: Takumi Mikawa, Yuji Judai, Yoshihisa Nagano
  • Patent number: 6143597
    Abstract: A method of manufacturing a capacitor comprises a step of forming a first dielectric layer composed of a ferroelectric material or a dielectric material possessing high permittivity on a first electrode, a step of sintering the first dielectric layer, a step of forming a second dielectric layer on the first dielectric layer, and a step of forming a second electrode on the second dielectric layer. By forming the second dielectric layer having small crystal grain size on the first dielectric layer having large crystal grain size, the surface of the capacitor insulating layer becomes flat.
    Type: Grant
    Filed: July 12, 1996
    Date of Patent: November 7, 2000
    Assignee: Matsushita Electronics Corporation
    Inventors: Akihiro Matsuda, Yoshihisa Nagano, Toru Nasu, Koji Arita, Yasuhiro Uemoto
  • Patent number: 6107657
    Abstract: A semiconductor device forming a capacitor through an interlayer insulating layer on a semiconductor substrate on which an integrated circuit is formed. This semiconductor device has an interlayer insulating layer with moisture content of 0.5 g/cm.sup.3 or less, which covers the capacitor in one aspect, and has a passivation layer with hydrogen content of 10.sup.21 atoms/cm.sup.3 or less, which covers the interconnections of the capacitor in other aspect. By thus constituting, deterioration of the capacitor dielectric can be prevented which brings about the electrical reliability of the ferroelectric layer or high dielectric layer.
    Type: Grant
    Filed: May 4, 1998
    Date of Patent: August 22, 2000
    Assignee: Matsushita Electronics Corporation
    Inventors: Koji Arita, Eiji Fujii, Yasuhiro Shimada, Yasuhiro Uemoto, Toru Nasu, Akihiro Matsuda, Yoshihisa Nagano, Atsuo Inoue, Taketoshi Matsuura, Tatsuo Otsuki
  • Patent number: 6100100
    Abstract: The method of this invention provides a method for manufacturing a capacitor element composed of films. The films have a precise etched shape without a residue that may be generated as a reaction product in a dry-etching process. In this invention, washing in a non-oxidizing atmosphere, inclining a side of a mask for etching or heating a substrate prevents the reaction product from remaining on the film as a residue. The reaction product can be washed away with water, acid or organic solvent in inert gas. The reaction product can be removed from the side of the mask by sputter-etching with ions for dry-etching. The reaction product can be exhausted without adhering to the mask by heating the substrate at a temperature between 100.degree. C. and 400.degree. C.
    Type: Grant
    Filed: July 24, 1998
    Date of Patent: August 8, 2000
    Assignee: Matsushita Electronics Corporation
    Inventors: Yoshihisa Nagano, Yasuhiro Shimada, Eiji Fujii
  • Patent number: 6046467
    Abstract: A capacitor 25 is formed on an insulating layer 21a formed on a semiconductor substrate 21. The end portion of a capacitor insulating layer 23 is positioned between the end portion of a bottom electrode 22 and the end portion of a top electrode 24. A passivation layer 26 for covering the capacitor 25 is formed. Interconnections 28 are connected to the bottom electrode 22 through a first hole 27a and to the top electrode 24 through a second hole 27b. In this way, since the end portion of the capacitor insulating layer 23 is out of the end portion of the top electrode 24, the end portion of the capacitor insulating layer 23 injured by etching does not affect the capacitance.
    Type: Grant
    Filed: June 20, 1996
    Date of Patent: April 4, 2000
    Assignee: Matsushita Electronics Corporation
    Inventors: Koji Arita, Akihiro Matsuda, Yoshihisa Nagano, Toru Nasu, Eiji Fujii
  • Patent number: 6046490
    Abstract: A semiconductor device is provided with a multilayered interconnection and a capacitor dielectric element, in which the transistor in the device has a non-degraded characteristics and the degradation of the capacitor dielectric element is suppressed. The semiconductor device has wiring layers connecting to one another through contact holes in insulating layers. One of the insulating layers is formed so as to cover at least a part of the area above the transistor and so as not to cover the area above the capacitor dielectric element. Hydrogen generated by heat-treating the insulating layer is supplied to the transistor to recover the damage in it, while hydrogen is suppressed from arriving at the capacitor element so that the capacitor dielectric element does not degrade.
    Type: Grant
    Filed: August 10, 1998
    Date of Patent: April 4, 2000
    Assignee: Matsushita Electronics Corporation
    Inventors: Koji Arita, Eiji Fujii, Yasuhiro Uemoto, Yoshihisa Nagano, Akihiro Matsuda
  • Patent number: 6015987
    Abstract: A semiconductor device forming a capacitor through an interlayer insulating layer on a semiconductor substrate on which an integrated circuit is formed. This semiconductor device has an interlayer insulating layer with moisture content of 0.5 g/cm.sup.3 or less, which covers the capacitor in one aspect, and has a passivation layer with hydrogen content of 10.sup.21 atoms/cm.sup.3 or less, which covers the interconnections of the capacitor in other aspect. By thus constituting, deterioration of the capacitor dielectric can be prevented which brings about the electrical reliability of the ferroelectric layer or high dielectric layer.
    Type: Grant
    Filed: May 4, 1998
    Date of Patent: January 18, 2000
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Koji Arita, Eiji Fujii, Yasuhiro Shimada, Yasuhiro Uemoto, Toru Nasu, Akihiro Matsuda, Yoshihisa Nagano, Atsuo Inoue, Taketoshi Matsuura, Tatsuo Otsuki