Abstract: A method for fabricating a capacitor for an integrated circuit, comprising the steps of forming a titanium film for an adhesion layer over a substrate, forming a titanium dioxide film for a diffusion barrier layer by annealing the titanium film after ion-implantation of oxygen ion into a surface region of the titanium film so as to change titanium in the surface region to titanium dioxide, and forming a high dielectric constant capacitor on the titanium dioxide film.

Abstract: A device insulating film, a lower-layer platinum film, a ferroelectric film, an upper-layer platinum film, and a titanium film are sequentially formed on a semiconductor substrate in this order. On the titanium film, a photoresist mask is further formed in a desired pattern. The thickness of the titanium film is adjusted to be 1/10 or more of the total thickness of a multilayer film consisting of the upper-layer platinum film, the ferroelectric film, and the lower-layer platinum film. The titanium film is then subjected to dry etching and the photoresist film is removed by ashing process. The titanium film thus patterned is used as a mask in etching the upper-layer platinum film, the ferroelectric film, and the lower-layer platinum film by a dry-etching method using a plasma of a gas mixture of chlorine and oxygen in which the volume concentration of oxygen gas is adjusted to be 40%. During the dry-etching process, the titanium film is oxidized to provide a high etching selectivity.

Abstract: A semiconductor device comprises silicon substrate 1 on which an integrated circuit is formed, first insulating layer 6 formed on silicon substrate 1, a capacitor comprising lower electrode 7 formed on first insulating layer 6, dielectric film 8 having a high dielectric constant and upper electrode 9, a second insulating film 11 having contact holes 13 which lead to lower electrode 7 and upper electrode 9 independently, diffusion barrier layer 17 which touches lower electrode 7 and upper electrode 9 at bottom of contact holes 13, and interconnection layer 15 formed on diffusion barrier layer 17. In diffusion barrier layer 17 at the bottom of contact hole 13, a lamellar region made of granular crystal is formed.

Abstract: The present invention relates to method of manufacturing semiconductor devices having built-in capacitor comprising a dielectric substance of high dielectric constant or a ferroelectric substance as the capacitance insulation film, and aims to solve a problem that the prior art capacitance insulation film contained in semiconductor devices has a rough surface which results in a poor insulating voltage and a large spread in electrical characteristics, as well as broken connection wire; in which method a capacitance insulation film is produced by first forming a first dielectric film, and forming a second dielectric film on the first dielectric film for a thickness greater than the difference in level between top and bottom of the surface of first dielectric film, and forming a thin film whose etching speed is identical with that of the second dielectric film on the second dielectric film making the surface of thin film flat, and then etching the whole of the thin film and part of the second dielectric film off

Abstract: A semi conductor device forming a capacitor through an interlayer insulating layer on a semiconductor substrate on which an integrated circuit is formed. This semiconductor device has an interlayer insulating layer with moisture content of 0.5 g/cm.sup.3 or less, which covers the capacitor in one aspect, and has a passivation layer with hydrogen content of 10.sup.21 atoms/cm.sup.3 or less, which covers the interconnections of the capacitor in other aspect. By thus constituting, deterioration of the capacitor dielectric can be prevented which brings about the electrical reliability of the ferroelectric layer or high dielectric layer.

Abstract: A platinum bottom electrode film, a dielectric film composed of a high permittivity dielectric material or a ferroelectric material, and a platinum top electrode film are formed on a substrate on which circuit elements and wiring are formed, and the platinum top electrode film and the dielectric film are selectively dry-etched by using etching gas containing chlorine, then plasma generated by discharging gas containing fluorine is irradiated. By this method of manufacturing a semiconductor device including a capacitor, there is almost no residual chlorine, and hence erosion of the dielectric film by residual chlorine is prevented.

Abstract: A semiconductor device comprises silicon substrate 1 on which an integrated circuit is formed, first insulating layer 6 formed on silicon substrate 1, a capacitor comprising lower electrode 7 formed on first insulating layer 6, dielectric film 8 having a high dielectric constant and upper electrode 9, a second insulating film 11 having contact holes 13 which lead to lower electrode 7 and upper electrode 9 independently, diffusion barrier layer 17 which touches lower electrode 7 and upper electrode 9 at the bottom of contact holes 13, and interconnection layer 15 formed on diffusion barrier layer 17. In diffusion barrier layer 17 at the bottom of contact hole 13, a lamellar region made of granular crystal is formed.

Abstract: A semiconductor device forming a capacitor through an interlayer insulating layer on a semiconductor substrate on which an integrated circuit is formed. This semiconductor device has an interlayer insulating layer with moisture content of 0.5 g/cm.sup.3 or less, which covers the capacitor in one aspect, and has a passivation layer with hydrogen content of 10.sup.21 atoms/cm.sup.3 or less, which covers the interconnections of the capacitor in other aspect. By thus constituting, deterioration of the capacitor dielectric can be prevented which brings about the electrical reliability of the ferroelectric layer or high dielectric layer.

Abstract: On a silicon substrate, a silicon oxide layer, a first platinum layer, a dielectric film and a second platinum layer are formed, and then the second platinum layer and the dielectric film are dry etched, via a resist layer, in a 1-5 Pa low pressure region with a mixed gas of HBr and 0.sub.2 as the etching gas. As soon as the first platinum layer is exposed, the unetched portion of dielectric film is etched off in a 5-50 Pa high pressure region, and then the first platinum layer is dry etched again in the low pressure region to form a capacitor consisting of a top electrode, a capacitance insulation layer and a bottom electrode in a semiconductor integrated circuit chip. Using this manufacturing method prevents the deterioration in definition caused by the use of a thick resist and the operation failure of circuit elements such as transistors due to over etching on the insulation layer.

Abstract: A manufacturing method of a semiconductor device comprises the steps:(a) forming a ferroelectric capacitor on a semiconductor substrate on which a MOS transistor is formed, (b) forming an interlayer insulating film which covers the whole semiconductor substrate, (c) forming first contact holes which reach diffusion layers of the MOS transistor, (d) after forming the first contact holes, providing a heat treatment in hydrogen atmosphere, (e) after the heat treatment, forming second contact holes which reach upper and lower electrodes of the ferroelectric capacitor on the interlayer insulating film, and (f) forming metal interconnection. Since the heat treatment in hydrogen atmosphere is provided before forming the second contact holes, a surface state density at interface between the semiconductor and a gate insulating film of the MOS transistor can be lowered without degrading the characteristics of ferroelectric capacitor.

Abstract: On a silicon substrate, a silicon oxide layer, a first platinum layer, a dielectric film and a second platinum layer are formed, and then the second platinum layer and the dielectric film are dry etched, via a resist layer, in a 1-5 Pa low pressure region with a mixed gas of HBr and O.sub.2 as the etching gas. As soon as the first platinum layer is exposed, the unetched portion of dielectric film is etched off in a 5-50 Pa high pressure region, and then the first platinum layer is dry etched again in the low pressure region to form a capacitor consisting of a top electrode, a capacitance insulation layer and a bottom electrode in a semiconductor integrated circuit chip. Using this manufacturing method prevents the deterioration in definition caused by the use of a thick resist and the operation failure of circuit elements such as transistors due to over etching on the insulation layer.

Abstract: A semiconductor memory device comprising bit line, word line, plate electrode, ferroelectric capacitor having first electrode and second electrode, said second electrode being coupled to said plate electrode, MOS transistor the source of which is coupled to said first electrode, the gate is coupled to said word line and the drain is coupled to said bit line, and adjusting capacitor for adjusting bit line capacitance coupled to said bit line. The adjusting capacitor is provided to increase the potential difference for reading and control occurrence of operating errors.