Patents by Inventor Yoshiji Ohta

Yoshiji Ohta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9590617
    Abstract: A semiconductor device includes a high breakdown voltage, high Gm first transistor and a low breakdown voltage, low Gm second transistor connected in series between first and second nodes, and a low breakdown voltage, high Gm third transistor connected to the second transistor in parallel. When the second transistor is turned on, the first transistor turns on, and furthermore, when the third transistor is turned on, an electrically conducting state is established between the first and second nodes. The second, low breakdown voltage transistor is turned on to turn on the first, high breakdown voltage transistor, and a turn-on time with only limited variation can be achieved.
    Type: Grant
    Filed: April 5, 2012
    Date of Patent: March 7, 2017
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Kenji Komiya, Shuji Wakaiki, Kohtaroh Kataoka, Masaru Nomura, Yoshiji Ohta, Hiroshi Iwata
  • Patent number: 9490381
    Abstract: Disclosed is a photovoltaic device 1 including a plurality of cluster power generation sections G (G11, G12, G21, and G22). Each cluster power generation section G includes unitary power generation sections D (D1, D2) connected in series via connection points CP12. The cluster power generation sections G each have at least a predetermined one of the connection points CP12 designated as a specific connection point SP12. The specific connection points SP12 are connected together to link the cluster power generation sections G.
    Type: Grant
    Filed: December 16, 2011
    Date of Patent: November 8, 2016
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Kohtaroh Kataoka, Kohichiroh Adachi, Masatomi Harada, Yoshiji Ohta, Hiroshi Iwata
  • Patent number: 9293984
    Abstract: In order to offer a power supply circuit that can minimize the drop in efficiency by reducing losses during voltage conversion, in an improved-power factor circuit, a control circuit performs a step-up operation in which a control signal for turning on a first switching element (Tr1) and switching a second switching element (Tr2) is output, and a step-down operation in which a control signal for turning off the second switching element (Tr2) and switching the first switching element (Tr1) is output.
    Type: Grant
    Filed: August 29, 2012
    Date of Patent: March 22, 2016
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Kenji Komiya, Takeshi Shiomi, Yoshifumi Yaoi, Masaru Nomura, Kohichiroh Adachi, Yoshiji Ohta, Hiroshi Iwata
  • Patent number: 9261259
    Abstract: A headlamp (1) that utilizes a laser beam includes a scattered-light emitting unit (21) that emits scattered light upon receipt of a laser beam deviated from a predetermined path through which the laser beam is to pass or a predetermined irradiation region that is to be irradiated by the laser beam.
    Type: Grant
    Filed: May 25, 2012
    Date of Patent: February 16, 2016
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Takeshi Shiomi, Masaru Nomura, Yoshiji Ohta, Hiroshi Iwata, Koji Takahashi, Katsuhiko Kishimoto
  • Patent number: 9214783
    Abstract: A light emitting device which includes at least one of a laser light source (1), wiring (9), a lens for excitation (2), a luminous body (4), a laser cut filter (6), a half parabolic mirror (5P), and a base (5h), in which a part of the wiring (9) is installed at a portion in which a breakage easily occurs due to at least one deformation of the laser light source (1), the lens for excitation (2), the luminous body (4), the laser cut filter (6), the half parabolic mirror (5P), and the base (5h), or a change in an installation position thereof.
    Type: Grant
    Filed: March 5, 2012
    Date of Patent: December 15, 2015
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Masaru Nomura, Yoshifumi Yaoi, Kohichiroh Adachi, Kohtaroh Kataoka, Takeshi Shiomi, Hiroshi Iwata, Yoshiji Ohta
  • Patent number: 9085239
    Abstract: A push-pull circuit comprising: a push-pull first switching element and second switching element; a first rectifier element; a third switching element for switching a pathway between conductance and cutoff, the pathway leading from a connection point between the first switching element and an inductive load via the first rectifier element to a connection point between a DC power source and a center tap of the inductive load; a second rectifier element; and a fourth switching element for switching a pathway between conductance and cutoff, the pathway leading from a connection point between the second switching element and the inductive load via the second rectifier element to a connection point between the DC power source and the center tap of the inductive load.
    Type: Grant
    Filed: September 7, 2012
    Date of Patent: July 21, 2015
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Kenji Kimoto, Hiroshi Igarashi, Yoshifumi Yaoi, Kenji Komiya, Masaru Nomura, Yoshiji Ohta, Hiroshi Iwata
  • Patent number: 9079501
    Abstract: A vehicle driving device is arranged such that in accordance with an instruction signal from the outside, a first battery managing section outputs, to the outside, a signal related to charging/discharging control for a first battery.
    Type: Grant
    Filed: August 27, 2012
    Date of Patent: July 14, 2015
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Kenji Komiya, Akihide Shibata, Masaru Nomura, Yoshiji Ohta, Hiroshi Iwata
  • Patent number: 9071154
    Abstract: This DC/DC converter includes a first DC/DC converter, and a second DC/DC converter for carrying out a DC/DC conversion of voltage supplied from the first DC/DC converter. One of either the first DC/DC converter or the second DC/DC converter is a fixed-factor DC/DC converter, and the other of either the first DC/DC converter or the second DC/DC converter is a variable-factor DC/DC converter.
    Type: Grant
    Filed: October 31, 2012
    Date of Patent: June 30, 2015
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Hiroshi Iwata, Yoshifumi Yaoi, Kenji Komiya, Masaru Nomura, Yoshiji Ohta
  • Patent number: 8901860
    Abstract: A photovoltaic apparatus according to the present invention includes a photovoltaic module and a tracking control device. The photovoltaic module includes a plurality of series portions coupled in parallel. The series portion includes a plurality of photovoltaic elements coupled in series. The photovoltaic elements coupled in a same straight row of the plurality of series portions are coupled parallel to one another. The tracking control device is configured to perform a maximum power point tracking control on an output of the photovoltaic module. The photovoltaic module includes a temperature sensor that detects a real panel temperature that is a panel temperature when the photovoltaic module is operating.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: December 2, 2014
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yoshifumi Yaoi, Kohtaroh Kataoka, Masatomi Harada, Kohichiroh Adachi, Yoshiji Ohta, Hiroshi Iwata
  • Publication number: 20140168940
    Abstract: A headlamp (1) that utilizes a laser beam includes a scattered-light emitting unit (21) that emits scattered light upon receipt of a laser beam deviated from a predetermined path through which the laser beam is to pass or a predetermined irradiation region that is to be irradiated by the laser beam.
    Type: Application
    Filed: May 25, 2012
    Publication date: June 19, 2014
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Takeshi Shiomi, Masaru Nomura, Yoshiji Ohta, Hiroshi Iwata, Koji Takahashi, Katsuhiko Kishimoto
  • Publication number: 20140028375
    Abstract: A semiconductor device includes a high breakdown voltage, high Gm first transistor and a low breakdown voltage, low Gm second transistor connected in series between first and second nodes, and a low breakdown voltage, high Gm third transistor connected to the second transistor in parallel. When the second transistor is turned on, the first transistor turns on, and furthermore, when the third transistor is turned on, an electrically conducting state is established between the first and second nodes. The second, low breakdown voltage transistor is turned on to turn on the first, high breakdown voltage transistor, and a turn-on time with only limited variation can be achieved.
    Type: Application
    Filed: April 5, 2012
    Publication date: January 30, 2014
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Kenji Komiya, Shuji Wakaiki, Kohtaroh Kataoka, Masaru Nomura, Yoshiji Ohta, Hiroshi Iwata
  • Publication number: 20140009952
    Abstract: A light emitting device which includes at least one of a laser light source (1), wiring (9), a lens for excitation (2), a luminous body (4), a laser cut filter (6), a half parabolic mirror (5P), and a base (5h), in which a part of the wiring (9) is installed at a portion in which a breakage easily occurs due to at least one deformation of the laser light source (1), the lens for excitation (2), the luminous body (4), the laser cut filter (6), the half parabolic mirror (5P), and the base (5h), or a change in an installation position thereof.
    Type: Application
    Filed: March 5, 2012
    Publication date: January 9, 2014
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Masaru Nomura, Yoshifumi Yaoi, Kohichiroh Adachi, Kohtaroh Kataoka, Takeshi Shiomi, Hiroshi Iwata, Yoshiji Ohta
  • Publication number: 20130240012
    Abstract: A photovoltaic system includes multiple series module units in each of which multiple photovoltaic modules are connected in series, multiple photovoltaic elements being implemented on a module implementation unit in each of the photovoltaic modules. The series module units are connected to each other in parallel, and the photovoltaic modules arranged in a same series stage are connected to each other in parallel.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 19, 2013
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Yoshifumi YAOI, Kohtaroh Kataoka, Kohichiroh Adachi, Masatomi Harada, Yoshiji Ohta, Hiroshi Iwata
  • Publication number: 20130240013
    Abstract: A photovoltaic power generation module includes: a plurality of rectangular photovoltaic power generation elements that are arranged such that long sides of perimeters of the elements are parallel; and an extension wiring that is extended in a short side direction intersecting the long sides and that interconnects the photovoltaic power generation elements, and the extension wiring connects every specified number of the photovoltaic power generation elements in parallel.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 19, 2013
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Yoshifumi Yaoi, Kohtaroh Kataoka, Kohichiroh Adachi, Masatomi Harada, Yoshiji Ohta, Hiroshi Iwata
  • Publication number: 20130241448
    Abstract: A photovoltaic apparatus according to the present invention includes a photovoltaic module and a tracking control device. The photovoltaic module includes a plurality of series portions coupled in parallel. The series portion includes a plurality of photovoltaic elements coupled in series. The photovoltaic elements coupled in a same straight row of the plurality of series portions are coupled parallel to one another. The tracking control device is configured to perform a maximum power point tracking control on an output of the photovoltaic module. The photovoltaic module includes a temperature sensor that detects a real panel temperature that is a panel temperature when the photovoltaic module is operating.
    Type: Application
    Filed: March 18, 2013
    Publication date: September 19, 2013
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Yoshifumi YAOI, Kohtaroh KATAOKA, Masatomi HARADA, Kohichiroh ADACHI, Yoshiji OHTA, Hiroshi IWATA
  • Patent number: 8508978
    Abstract: A semiconductor memory device includes a memory cell array in which a plurality of memory cells is aligned in a matrix shape, each memory cell including a two-terminal memory element and a transistor for selection connected in series; a first voltage applying circuit that applies a writing voltage pulse to first bit lines; and a second voltage applying circuit that applies a pre-charge voltage to the first bit lines and second bit lines, wherein in a writing of a memory cell, after the second voltage applying circuit has pre-charged both ends of the memory cell to a same voltage, the first voltage applying circuit applies the writing voltage pulse via the first bit line that is directly connected to the transistor for selection, and the second voltage applying circuit applies the pre-charge voltage to the second bit line directly connected to the memory element.
    Type: Grant
    Filed: May 24, 2011
    Date of Patent: August 13, 2013
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Kazuya Ishihara, Mitsuru Nakura, Yoshiji Ohta
  • Patent number: 8482956
    Abstract: A semiconductor memory device includes a memory cell array where a plurality of memory cells are arranged in a matrix, each of the memory cells serially connecting a two-terminal type memory element and a transistor for selection, a first voltage applying circuit that applies a write voltage pulse to a bit line, and a second voltage applying circuit that applies a precharge voltage to a bit line and a common line. In writing the memory cell, after the second voltage applying circuit has both terminals of the memory cell previously precharged to the same voltage, the first voltage applying circuit applies the write voltage pulse to one terminal of the writing target memory cell via the bit line, and while the write voltage pulse is applied, the second voltage applying circuit maintains the application of the precharge voltage to the other terminal of the memory cell via the common line.
    Type: Grant
    Filed: July 11, 2011
    Date of Patent: July 9, 2013
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Shinobu Yamazaki, Yoshiji Ohta, Kazuya Ishihara, Mitsuru Nakura, Suguru Kawabata, Nobuyoshi Awaya
  • Patent number: 8450713
    Abstract: A three-dimensional memory cell array of memory cells with two terminals having a variable resistive element is formed such that: one ends of memory cells adjacent in Z direction are connected to one of middle selection lines extending in Z direction aligned in X and Y directions; the other ends of the memory cells located at the same point in Z direction are connected to one of third selection lines aligned in Z direction; a two-dimensional array where selection transistors are aligned in X and Y directions is adjacent to the memory cell array in Z direction; gates of selection transistors adjacent in X direction, drains of selection transistors adjacent in Y direction and sources of selection transistors are connected to same first selection line, second selection line, and different middle selection lines, respectively; and first, second and third selection lines are connected to X, Y and Z decoders, respectively.
    Type: Grant
    Filed: February 26, 2010
    Date of Patent: May 28, 2013
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Nobuyoshi Awaya, Yoshiji Ohta, Yoshiaki Tabuchi
  • Publication number: 20130106342
    Abstract: This DC/DC converter includes a first DC/DC converter, and a second DC/DC converter for carrying out a DC/DC conversion of voltage supplied from the first DC/DC converter. One of either the first DC/DC converter or the second DC/DC converter is a fixed-factor DC/DC converter, and the other of either the first DC/DC converter or the second DC/DC converter is a variable-factor DC/DC converter.
    Type: Application
    Filed: October 31, 2012
    Publication date: May 2, 2013
    Inventors: Hiroshi IWATA, Yoshifumi YAOI, Kenji KOMIYA, Masaru NOMURA, Yoshiji OHTA
  • Patent number: 8422270
    Abstract: A nonvolatile semiconductor memory device includes a bit voltage adjusting circuit which, for each bit line, fixes potentials of a selected bit line and a non-selected bit line to a predetermined potential to perform a memory operation and a data voltage adjusting circuit which, for each data line, fixes potentials of a selected data line and a non-selected data line to a predetermined potential to perform a memory operation. Each of the voltage adjusting circuits includes an operational amplifier and a transistor, a voltage required for a memory operation is input to the non-inverted input terminal of the operational amplifier, and the inverted input terminal of the operational amplifier is connected to the bit line or the data line, so that the potential of the bit line or the data line is fixed to a potential of the non-inverted input terminal of the operational amplifier.
    Type: Grant
    Filed: March 10, 2011
    Date of Patent: April 16, 2013
    Assignees: Sharp Kabushiki Kaisha, National University Corporation Kanazawa University
    Inventors: Suguru Kawabata, Shinobu Yamazaki, Yoshiji Ohta, Kazuya Ishihara, Nobuyoshi Awaya, Akio Kitagawa, Kazuya Nakayama