Patents by Inventor Yoshiji Ohta
Yoshiji Ohta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7584084Abstract: A numerical model related to fluttering of an insect, when an equivalent model of actual structure of a wing of the insect is moved in the air in accordance with a model of fluttering motion of the wing of the insect is calculated by fluid-structure interactive analysis, in which behavior of the wing and behavior of the air are given as numerical values, including interaction therebetween. Thereafter, a method of controlling a fluttering robot, wing shape and the like are determined by modifying numerical models of fluttering of an insect prepared by fluid-structure interactive analysis, in accordance with sensitivity analysis. Accordingly, a method of preparing numerical models of wing and air considering the behavior of the wing of the insect in the air is provided and, in addition, a method of manufacturing a fluttering robot utilizing the numerical model prepared by this method of preparing numerical model can be provided.Type: GrantFiled: November 19, 2002Date of Patent: September 1, 2009Assignee: Sharp Kabushiki KaishaInventors: Masaki Hamamoto, Yoshiji Ohta, Keita Hara, Toshiaki Hisada
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Publication number: 20090073158Abstract: A memory element having a large memory window and a high reliability is provided at low cost by performing high speed write and erase operations at a relatively low voltage and suppressing rewrite degradation. A memory element includes a semiconductor layer arranged on an insulating substrate, a first diffusion layer region and a second diffusion layer region having a conductivity type of P-type, a charge accumulating film for covering a channel region between the first diffusion layer region and the second diffusion layer region and being injected with charges from the channel region, and a gate electrode positioned on a side opposite to the channel region with the charge accumulating film in between.Type: ApplicationFiled: September 17, 2008Publication date: March 19, 2009Applicant: SHARP KABUSHIKI KAISHAInventors: Kotaro Kataoka, Hiroshi Iwata, Yoshiji Ohta, Kenji Kimoto, Kenji Komiya, Kouichiro Adachi, Akihide Shibata, Masatomi Harada
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Patent number: 7474256Abstract: A transmitting apparatus and a receiving apparatus of a position detecting system execute a program including the steps of transmitting a laser beam; detecting an azimuth ?(Y) at which the laser beam is transmitted; detecting an azimuth ? at which the reflected laser beam is received; calculating a distance L(1) between the transmitting apparatus and a moving body from ?(Y), ? and a distance D between the transmitting apparatus and the receiving apparatus; and calculating a distance L(2) between the receiving apparatus and the moving body.Type: GrantFiled: August 12, 2004Date of Patent: January 6, 2009Assignee: Sharp Kabushiki KaishaInventors: Yoshiji Ohta, Keita Hara, Masaki Hamamoto
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Patent number: 7457164Abstract: In the semiconductor storage device, in a read operation, a bit line charging/discharging section 101 performs discharge of bit lines of a memory cell array 100, and a counter counts discharge periods over which the potentials of bit lines come to a specified potential, based on a comparison result of a comparator comparing a potential of a bit line with a reference potential. Based on the comparison result, a reference value generation section 104 generates a reference value (RCi) for determining information stored in each of the memory cells. The above count value (CBUSi) and the above reference value (RCi) are compared with each other by a data decision circuit 108. Based on the comparison result, an output data control circuit 109 outputs information stored in each of the memory cells. This semiconductor storage device suppresses increases in chip area and power consumption and outputs memory cell information accurately.Type: GrantFiled: October 3, 2006Date of Patent: November 25, 2008Assignee: Sharp Kabushiki KaishaInventor: Yoshiji Ohta
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Publication number: 20080247232Abstract: A semiconductor storage device includes a first memory cell for storing two kinds of states, a second memory cell for storing two kinds of states, and a sense amplifier for detecting a potential difference between voltages equivalent to readout currents of the first and second memory cells, respectively. Either one of information data “0” or data “1”, which is stored in combination of the first and second memory cells, is read out by detecting the potential difference equivalent to the readout current difference between the first and second memory cells.Type: ApplicationFiled: March 20, 2008Publication date: October 9, 2008Applicant: SHARP KABUSHIKI KAISHAInventors: Hiroshi Iwata, Yoshiji Ohta
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Patent number: 7409266Abstract: A group robot system includes a plurality of sensing robots and a base station controlling the sensing robots, and establishes communication in a hierarchical manner. The hierarchical structure is formed of a plurality of levels between a plurality of sensing robots with base station as the highest hierarchical level. The first sensing robot detects an object; the second sensing robot conducts further search on the object; and the third sensing robot conducts communication relay between the first sensing robot and the base station. When the first sensing robot detects an object, the base station provides control such that all sensing robots, other than the first, second and third sensing robots, move outside the current area of search.Type: GrantFiled: December 17, 2003Date of Patent: August 5, 2008Assignee: Sharp Kabushiki KaishaInventors: Keita Hara, Masaki Hamamoto, Yoshiji Ohta
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Patent number: 7385848Abstract: A semiconductor storage device has a memory cell array composed of a plurality of arrayed memory cells, word lines, bit lines, a bit line charging and discharging circuit, and a readout section. Each memory cell has two storage regions in vicinity of opposite ends of a channel region, first and second input/output terminals, and a control terminal. The readout section reads information stored in one of the first and second storage regions of a memory cell based on a first output equivalent to an output current from the memory cell when a current is passed from the first input/output terminal to the second input/output terminal of the memory cell and a second output equivalent to an output current from the memory cell when a current is passed from the second input/output terminal to the first input/output terminal.Type: GrantFiled: September 7, 2006Date of Patent: June 10, 2008Assignee: Sharp Kabushiki KaishaInventors: Hiroshi Iwata, Yoshiji Ohta
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Publication number: 20080037332Abstract: A semiconductor storage device is capable of discriminating information stored in memory cells with high accuracy even if a gap that separates distributions of cell current values between data 0 and data 1 among a plurality of memory cells in a memory cell array becomes extremely narrow or overlapped with each other. A first memory cell MC11 and a second memory cell MC2 are adjacent to each other, and a first bit line BL1 to which a first input/output terminal of the first memory cell MC11 is connected as well as a second bit line BL2 to which a second input/output terminal of the second memory cell MC12 is connected are connected to inputs of a sense amplifier SA1, respectively. A second input/output terminal of the first memory cell MC11 and a first input/output terminal of the second memory cell MC12 are connected to a common line COM.Type: ApplicationFiled: August 9, 2007Publication date: February 14, 2008Inventor: Yoshiji OHTA
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Patent number: 7289371Abstract: A semiconductor memory device has a memory cell array in which a plurality of nonvolatile memory cells are arranged. The memory device also has word lines, bit lines connected with the memory cells by a virtual grounding scheme, a row decoder, shift registers, a write voltage control circuit for controlling voltages to be applied to bit lines, and a write voltage applying circuit for applying voltages to the bit lines. The write voltage control circuit controls the write voltage applying circuit such that when writing data 1 to a memory cell, different voltages V0 and VP are applied to two bit lines associated with the memory cell, while a same voltage V0 or VP is applied to the two bit lines when writing data 0 to the memory cell.Type: GrantFiled: April 11, 2006Date of Patent: October 30, 2007Assignee: Sharp Kabushiki KaishaInventor: Yoshiji Ohta
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Patent number: 7283893Abstract: Communication system of a group robot system is made hierarchical, having a base station as an uppermost layer and a plurality of layers formed by a plurality of sensing robots, and the plurality of sensing robots are controlled such that a sensing robot belonging to an upper layer of the hierarchical structure has higher sensing resolution than a sensing robot belonging to a lower layer of the hierarchical structure. Thus, a group robot system capable of efficiently searching for an object can be obtained.Type: GrantFiled: May 24, 2006Date of Patent: October 16, 2007Assignee: Sharp Kabushiki KaishaInventors: Keita Hara, Masaki Hamamoto, Yoshiji Ohta, Kenji Ohta
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Patent number: 7219855Abstract: A fluid-structure interactive analysis is performed while n types of wing structure models are caused to flap in accordance with a prescribed model of flapping manner. Based on an analysis, data 1, data 2, . . . data n of physical values related to fluid behavior and physical values related to structural behavior are calculated. Among data 1, data 2, . . . data n, a data having a prescribed parameter such as the lift force optimized is extracted. A prototype of a wing portion is formed, which has such a structure that is specified by various parameter values of the numerical model of wing structure corresponding to the extracted data. A driving unit 905 drives the prototype of the wing portion in a manner of flapping that is represented by the flapping motion model equivalent to the manner of flapping of an insect. At this time, the wing has a stiffness that is suitable for flapping flight so that prescribed parameters come to have optimal values.Type: GrantFiled: July 11, 2003Date of Patent: May 22, 2007Assignee: Sharp Kabushiki KaishaInventors: Masaki Hamamoto, Yoshiji Ohta, Keita Hara
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Publication number: 20070086238Abstract: In the semiconductor storage device, in a read operation, a bit line charging/discharging section 101 performs discharge of bit lines of a memory cell array 100, and a counter counts discharge periods over which the potentials of bit lines come to a specified potential, based on a comparison result of a comparator comparing a potential of a bit line with a reference potential. Based on the comparison result, a reference value generation section 104 generates a reference value (RCi) for determining information stored in each of the memory cells. The above count value (CBUSi) and the above reference value (RCi) are compared with each other by a data decision circuit 108. Based on the comparison result, an output data control circuit 109 outputs information stored in each of the memory cells. This semiconductor storage device suppresses increases in chip area and power consumption and outputs memory cell information accurately.Type: ApplicationFiled: October 3, 2006Publication date: April 19, 2007Inventor: Yoshiji Ohta
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Publication number: 20070076499Abstract: A semiconductor storage device has a memory cell array composed of a plurality of arrayed memory cells, word lines, bit lines, a bit line charging and discharging circuit, and a readout section. Each memory cell has two storage regions in vicinity of opposite ends of a channel region, first and second input/output terminals and a control terminal. The readout section reads information stored in one of the first and second storage regions of a memory cell based on a first output equivalent to an output current from the memory cell when a current is passed from the first input/output terminal to the second input/output terminal of the memory cell and a second output equivalent to an output current from the memory cell when a current is passed from the second input/output terminal to the first input/output terminal.Type: ApplicationFiled: September 7, 2006Publication date: April 5, 2007Inventors: Hiroshi Iwata, Yoshiji Ohta
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Patent number: 7195199Abstract: A flapping apparatus includes a first disk rotated by a driving source, and a second disk that rotates in contact with a main surface of the first disk. The second disk is provided with first and second stoppers that limit its angle of rotation. When the stopper is in contact with the first disk, rotation of a wing shaft is caused only by the rotation of the first disk, and when the stoppers are not in contact with the first disk, rotation of the wing shaft is caused only by the rotation of the second disk.Type: GrantFiled: April 15, 2005Date of Patent: March 27, 2007Assignee: Sharp Kabushiki KaishaInventors: Yoshiji Ohta, Keita Hara, Masaki Hamamoto
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Publication number: 20060239071Abstract: A semiconductor memory device has a memory cell array in which a plurality of nonvolatile memory cells are arranged. The memory device also has word lines, bit lines connected with the memory cells by a virtual grounding scheme, a row decoder, shift registers, a write voltage control circuit for controlling voltages to be applied to bit lines, and a write voltage applying circuit for applying voltages to the bit lines. The write voltage control circuit controls the write voltage applying circuit such that when writing data 1 to a memory cell, different voltages V0 and VP are applied to two bit lines associated with the memory cell, while a same voltage V0 or VP is applied to the two bit lines when writing data 0 to the memory cell.Type: ApplicationFiled: April 11, 2006Publication date: October 26, 2006Inventor: Yoshiji Ohta
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Publication number: 20060217843Abstract: Communication system of a group robot system is made hierarchical, having a base station as an uppermost layer and a plurality of layers formed by a plurality of sensing robots, and the plurality of sensing robots are controlled such that a sensing robot belonging to an upper layer of the hierarchical structure has higher sensing resolution than a sensing robot belonging to a lower layer of the hierarchical structure. Thus, a group robot system capable of efficiently searching for an object can be obtained.Type: ApplicationFiled: May 24, 2006Publication date: September 28, 2006Applicant: Sharp Kabushiki KaishaInventors: Keita Hara, Masaki Hamamoto, Yoshiji Ohta, Kenji Ohta
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Patent number: 7089084Abstract: A search robot system first divides the entire area of disaster into a mesh cell of an appropriate size, and arranges a search robot for each mesh cell. A search is made for a route of travel from an outermost mesh cell to a casualty and to an adjacent mesh cell. The search robot immediately communicates with a mother robot when a casualty is found. The search robot also communicates with the mother robot when a route to an adjacent mesh cell is found. In the search robot system, a new search robot is arranged to search in an adjacent mesh cell. Accordingly, a rescue activity that is a matter of time can be carried out by a plurality of robots.Type: GrantFiled: May 27, 2003Date of Patent: August 8, 2006Assignee: Sharp Kabushiki KaishaInventors: Yoshiji Ohta, Masaki Hamamoto, Keita Hara
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Patent number: 7082351Abstract: Communication system of a group robot system is made hierarchical, having a base station as an uppermost layer and a plurality of layers formed by a plurality of sensing robots, and the plurality of sensing robots are controlled such that a sensing robot belonging to an upper layer of the hierarchical structure has higher sensing resolution than a sensing robot belonging to a lower layer of the hierarchical structure. Thus, a group robot system capable of efficiently searching for an object can be obtained.Type: GrantFiled: November 18, 2002Date of Patent: July 25, 2006Assignee: Sharp Kabushiki KaishaInventors: Keita Hara, Masaki Hamamoto, Yoshiji Ohta, Kenji Ohta
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Publication number: 20060060698Abstract: In a moving apparatus, flapping angle of a front wing shaft is ?+??/2, and the flapping angle of rear wing shaft is ????/2. Specifically, amplitude difference between front wing shaft and rear wing shaft is ??. Further, the flapping motion of front wing shaft is represented by sin (?+?p/2), and the flapping motion of rear wing shaft is represented by sin (???/2). In other words, phase difference between the front and rear wing shafts is ?. Further, amplitude difference ?? and phase difference ? are each represented by a function using a common parameter. Therefore, a control portion can independently change the amplitude difference ?? and phase difference ?, so as to variously change a torsion angle formed by a tip end portion of the wing and a prescribed phantom plane. Thus, a moving apparatus that can make an efficient transition from hovering to forward or backward flight can be provided.Type: ApplicationFiled: June 23, 2005Publication date: March 23, 2006Inventors: Yoshiji Ohta, Keita Hara, Masaki Hamamoto
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Publication number: 20050230523Abstract: A flapping apparatus includes a first disk rotated by a driving source, and a second disk that rotates in contact with a main surface of the first disk. The second disk is provided with first and second stoppers that limit its angle of rotation. When the stopper is in contact with the first disk, rotation of a wing shaft is caused only by the rotation of the first disk, and when the stoppers are not in contact with the first disk, rotation of the wing shaft is caused only by the rotation of the second disk.Type: ApplicationFiled: April 15, 2005Publication date: October 20, 2005Inventors: Yoshiji Ohta, Keita Hara, Masaki Hamamoto