Abstract: There is provided a serial access system semiconductor storage device capable of reducing access time and decreasing consumption current. A memory cell array including a plurality of memory cells and shift registers and having a plurality of latch circuits connected in series are provided. The shift registers once hold data, received from the memory cell array 1 via a bit line in a read operation, in the latch circuits and serially output the held data in the order in which the latch circuits are arranged. The latch circuits sense-amplify the data stored in the memory cells inside the memory cell array.

Abstract: An improved signal line system for lines such as bit lines for a semiconductor memory is disclosed. In the signal line system, a first pair of signal lines cross each other at at least one point. At least one portion of one of the signal lines of a second pair is disposed between the signal lines of the first pair. At least one portion of one of the signal lines of a third pair is disposed between one of the signal lines of the first pair and the one signal line of the second pair. At least one portion of one of the signal lines of a fourth pair is disposed to a side of the other one of the signal lines of the first pair. At least one portion of one of the signal lines of a fifth pair is disposed to a side of one of the signal lines of the first pair. The level of the crosstalk between the signal lines can be effectively reduced.

Abstract: A dynamic semiconductor memory device for storing a signal corresponding to two bits of digital data in a single memory cell. A memory cell consisting of two transistors and one capacitor is formed. Logic is provided to convert two bits of data to two levels of charge with two different polarities. The result is a memory device which requires only 11/2 elements per bit of storage in contrast to the two elements per bit of storage needed in conventional memory cells.

Abstract: A semiconductor memory device for storing data includes a plurality of cells (4) aligned horizontally and vertically; first bit lines (BL) connected to cells occurring in odd number locations of vertically aligned cells; second bit lines (BL#) connected to cells occurring in the even number locations of the vertically aligned cells; writing circuits (2); a precharge circuit (6); and, a writing control circuit (1). The writing circuit (2) simultaneously charges one of the bit lines to a predetermined voltage and maintains the other of the bit lines at a precharge voltage level. The write circuit control means (1) controls which of the bit lines is to be charged to the predetermined voltage level and which of the bit lines is to be maintained at the precharge voltage level, whereby common data is written to all memory cells (4) in a row when a word signal is activated on a word line connected to the row.

Abstract: A method of making a biologically inactive polypeptide active is disclosed. Activity is imparted to the polypeptide through treatment with an exogenous peptide sequence. The nature of the exogenous peptide sequence is disclosed.

Abstract: A dynamic semiconductor multi-value memory device has memory cells each of which includes a series circuit of one storage capacitor and two transistors. A first capacitor is connected between a first bit line of a first bit line pair and a second bit line of a second bit line pair which is adjacent to the first bit line pair. A second capacitor is connected between a second bit line of the first bit line pair and a first bit line of the second bit line pair.

Abstract: The secondary side of a control capacitor is charged, prior to the precharge period, almost to the source voltage level by a dummy cycle performed after power-on. Then, during the precharge period, a control circuit charges the control capacitor to increase the potential of its primary side to a level higher than the source voltage level V.sub.cc. The potential of the gate of the first transistor is increased to a level higher than the source voltage level, which causes the first transistor to turn on to charge a booster capacitor. At this time, since the secondary side of the booster capacitor is grounded through a third transistor, the primary side of the booster capacitor is held at the source voltage level. When the active period is entered, the third transistor is turned off, and a second transistor which is connected between the power source and the booster capacitor is turned on. This causes the potential of the secondary side of the booster capacitor to rise to the source voltage level.

Abstract: A semiconductor IC element is three-dimensionally structured with a first active layer formed on a single crystalline silicon substrate and a second active layer formed by melting polycrystalline silicon by irradiation on an insulative layer which electrically insulates it from the first layer. Each active layer is comprised of single crystalline areas where transistors may be formed and separation areas which insulate them. PMOS, NMOS or CMOS field effective transistors are formed on these active element areas. A test circuit for testing the originally intended functions of the element as well as its redundant circuits may be formed on these layers. Throughholes are provided to connect the vertically separated active layers.