Patents by Inventor Yoshikatsu Ishizuki
Yoshikatsu Ishizuki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10483195Abstract: A resin board includes: a resin layer and a through electrode buried in the resin layer, wherein the through electrode has an electrode surface exposed from a front surface or a back surface of the resin layer and a lateral surface, and the electrode surface and the lateral surface form an obtuse angle.Type: GrantFiled: June 12, 2017Date of Patent: November 19, 2019Assignee: FUJITSU LIMITEDInventors: Yasushi Kobayashi, Yoshihiro Nakata, Yoshikatsu Ishizuki, Daijiro Ishibashi, Shinya Sasaki
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Patent number: 10057995Abstract: An electronic device includes a resin layer, a conductive layer buried in the resin layer, an electronic part buried in the resin layer, and a wiring layer arranged on the resin layer, the wiring layer including wiring and an opening, the wiring being connected electrically to the conductive layer and the electronic part, the opening communicating with the conductive layer.Type: GrantFiled: July 23, 2015Date of Patent: August 21, 2018Assignee: FUJITSU LIMITEDInventors: Shinya Iijima, Yoshikatsu Ishizuki
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Publication number: 20180068787Abstract: An inductor apparatus includes: a substrate including an electrical insulation property and a non-magnetic material; and a plurality of inductors disposed in the substrate so as to extend from a first surface of the substrate to a second surface of the substrate, each of the plurality of inductors including: an inductor conductive part that has an electrical conductivity and extends in a thickness direction of the substrate; and a magnetic layer that covers a side of the inductor conductive part and include a relative permeability and a soft magnetic material.Type: ApplicationFiled: October 27, 2017Publication date: March 8, 2018Applicant: FUJITSU LIMITEDInventors: Hiroshi NAKAO, Yu Yonezawa, Takahiko Sugawara, Yoshiyasu Nakashima, Yoshikatsu Ishizuki, Shinya Sasaki, Shinya Iijima
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Patent number: 9888575Abstract: An electronic device includes: a wiring substrate;a plurality of components having different heights mounted on one surface of the wiring substrate; and a flexible substrate, the flexible substrate being formed by laminating on a one surface side of the wiring substrate, that covers the plurality of components, the flexible substrate including a first portion that covers, among the plurality of components, one or more first components that have heights that are equivalent to or lower than a first height, and a second portion that covers, among the plurality of components, one or more second components other than the one or more first components, a first rigidity of the first portion being higher than a second rigidity of the second portion.Type: GrantFiled: January 24, 2017Date of Patent: February 6, 2018Assignee: FUJITSU LIMITEDInventor: Yoshikatsu Ishizuki
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Publication number: 20170365545Abstract: A resin board includes: a resin layer and a through electrode buried in the resin layer, wherein the through electrode has an electrode surface exposed from a front surface or a back surface of the resin layer and a lateral surface, and the electrode surface and the lateral surface form an obtuse angle.Type: ApplicationFiled: June 12, 2017Publication date: December 21, 2017Applicant: FUJITSU LIMITEDInventors: Yasushi Kobayashi, Yoshihiro NAKATA, Yoshikatsu Ishizuki, Daijiro Ishibashi, Shinya Sasaki
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Patent number: 9837208Abstract: An inductor apparatus includes: a substrate including an electrical insulation property and a non-magnetic material; and a plurality of inductors disposed in the substrate so as to extend from a first surface of the substrate to a second surface of the substrate, each of the plurality of inductors including: an inductor conductive part that has an electrical conductivity and extends in a thickness direction of the substrate; and a magnetic layer that covers a side of the inductor conductive part and include a relative permeability and a soft magnetic material.Type: GrantFiled: November 13, 2014Date of Patent: December 5, 2017Assignee: FUJITSU LIMITEDInventors: Hiroshi Nakao, Yu Yonezawa, Takahiko Sugawara, Yoshiyasu Nakashima, Yoshikatsu Ishizuki, Shinya Sasaki, Shinya Iijima
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Publication number: 20170257948Abstract: An electronic device includes: a wiring substrate;a plurality of components having different heights mounted on one surface of the wiring substrate; and a flexible substrate, the flexible substrate being formed by laminating on a one surface side of the wiring substrate, that covers the plurality of components, the flexible substrate including a first portion that covers, among the plurality of components, one or more first components that have heights that are equivalent to or lower than a first height, and a second portion that covers, among the plurality of components, one or more second components other than the one or more first components, a first rigidity of the first portion being higher than a second rigidity of the second portion.Type: ApplicationFiled: January 24, 2017Publication date: September 7, 2017Applicant: FUJITSU LIMITEDInventor: yoshikatsu ishizuki
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Patent number: 9312151Abstract: A method of manufacturing a semiconductor device, includes: providing a first adhesive layer on a support member; providing a film on the first adhesive layer; arranging a semiconductor element on the film; providing a resin layer on the film on which the semiconductor element is arranged, and forming a substrate including the semiconductor element and the resin layer on the film; and separating the film and the substrate from the first adhesive layer.Type: GrantFiled: January 24, 2013Date of Patent: April 12, 2016Assignee: FUJITSU LIMITEDInventors: Shinya Sasaki, Yoshikatsu Ishizuki, Motoaki Tani
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Publication number: 20160088737Abstract: An electronic device includes a resin layer, a conductive layer buried in the resin layer, an electronic part buried in the resin layer, and a wiring layer arranged on the resin layer, the wiring layer including wiring and an opening, the wiring being connected electrically to the conductive layer and the electronic part, the opening communicating with the conductive layer.Type: ApplicationFiled: July 23, 2015Publication date: March 24, 2016Inventors: Shinya Iijima, yoshikatsu ishizuki
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Patent number: 9214361Abstract: A method of manufacturing a semiconductor device, includes: placing a semiconductor element on an adhesive layer that is placed on a support body having a first through hole; placing a part in an area that includes a portion corresponding to the first through-hole, the portion being on the adhesive layer placed on the support body; forming a substrate on the adhesive layer by forming a resin layer on the adhesive layer, on which the semiconductor element and the part have been placed, the substrate including the semiconductor element, the part, and the resin layer; and detaching the substrate from the adhesive layer by pressing the part through the first through-hole.Type: GrantFiled: January 24, 2013Date of Patent: December 15, 2015Assignee: FUJITSU LIMITEDInventors: Yoshikatsu Ishizuki, Shinya Sasaki, Motoaki Tani
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Patent number: 9136172Abstract: A method of manufacturing a semiconductor device, includes: providing an adhesive layer on a support body; providing a semiconductor element on the adhesive layer; providing a resin layer on the adhesive layer, the semiconductor element being provided on the adhesive layer, and forming a substrate on the adhesive layer, the substrate including the semiconductor element and the resin layer; and removing the substrate from the adhesive layer, wherein an adhesive force of the adhesive layer in a direction in which the substrate is removed is less than an adhesive force of the adhesive layer in a planar direction in which the substrate is formed.Type: GrantFiled: January 23, 2013Date of Patent: September 15, 2015Assignee: FUJITSU LIMITEDInventors: Motoaki Tani, Yoshikatsu Ishizuki, Shinya Sasaki
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Publication number: 20150200050Abstract: An inductor apparatus includes: a substrate including an electrical insulation property and a non-magnetic material; and a plurality of inductors disposed in the substrate so as to extend from a first surface of the substrate to a second surface of the substrate, each of the plurality of inductors including: an inductor conductive part that has an electrical conductivity and extends in a thickness direction of the substrate; and a magnetic layer that covers a side of the inductor conductive part and include a relative permeability and a soft magnetic material.Type: ApplicationFiled: November 13, 2014Publication date: July 16, 2015Inventors: Hiroshi NAKAO, Yu YONEZAWA, Takahiko SUGAWARA, Yoshiyasu NAKASHIMA, Yoshikatsu ISHIZUKI, Shinya SASAKI, Shinya IIJIMA
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Patent number: 8962470Abstract: A semiconductor substrate is secured by suction to a rear face of a supporting face of a substrate supporting table. In this event, the thickness of the semiconductor substrate is made fixed by planarization on the rear face, and the rear face is forcibly brought into a state free from undulation by the suction to the supporting face, so that the rear face becomes a reference face for planarization of a front face. In this state, a tool is used to cut surface layers of Au projections and a resist mask on the front face, thereby planarizing the Au projections and the resist mask so that their surfaces become continuously flat. This can planarize the surfaces of fine bumps formed on the substrate at a low cost and a high speed in place of CMP.Type: GrantFiled: March 30, 2009Date of Patent: February 24, 2015Assignee: Fujitsu LimitedInventors: Masataka Mizukoshi, Yoshikatsu Ishizuki, Kanae Nakagawa, Keishiro Okamoto, Kazuo Teshirogi, Taiji Sakai
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Patent number: 8704106Abstract: A method of manufacturing an electronic component includes forming a resin layer over an underlying layer, pressing a conductor plate including a pattern formed on one major surface thereof against the resin layer, and embedding the pattern in the resin layer, and performing polishing, Chemical Mechanical Polishing, or cutting by the use of a diamond bit on another major surface of the conductor plate until the resin layer appears, and leaving the pattern in the resin layer as a conductor pattern.Type: GrantFiled: May 23, 2011Date of Patent: April 22, 2014Assignee: Fujitsu LimitedInventors: Masataka Mizukoshi, Yoshikatsu Ishizuki
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Publication number: 20110220397Abstract: A method of manufacturing an electronic component includes forming a resin layer over an underlying layer, pressing a conductor plate including a pattern formed on one major surface thereof against the resin layer, and embedding the pattern in the resin layer, and performing polishing, Chemical Mechanical Polishing, or cutting by the use of a diamond bit on another major surface of the conductor plate until the resin layer appears, and leaving the pattern in the resin layer as a conductor pattern.Type: ApplicationFiled: May 23, 2011Publication date: September 15, 2011Applicant: FUJITSU LIMITEDInventors: Masataka Mizukoshi, Yoshikatsu Ishizuki
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Patent number: 7937830Abstract: An interposer 2 comprising a base 10 formed of a plurality of resin layers 26, 34, 42, 52, 56; a thin-film capacitor 12 buried in the base 10, including a lower electrode 20, a capacitor dielectric film 22 and an upper electrode 24; a first through-electrode 14b formed through the base 10 and electrically connected to the upper electrode 24 of the thin-film capacitor 12; and a second through-electrode 14a formed through the base 10 and electrically connected to the lower electrode 20 of the thin-film capacitor 12, further comprising: an interconnection 48 buried in the base 10 and electrically connected to the respective upper electrodes 24 of a plurality of the thin-film capacitors 12, a plurality of the first through-electrodes 14b being electrically connected to the upper electrodes 24 of said plurality of the thin-film capacitors 12 via the interconnection 48, and said plurality of the first through-electrodes 14b being electrically interconnected by the interconnections 48.Type: GrantFiled: June 18, 2008Date of Patent: May 10, 2011Assignee: Fujitsu LimitedInventors: Takeshi Shioga, Yoshikatsu Ishizuki, John David Baniecki, Kazuaki Kurihara
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Patent number: 7852439Abstract: The invention relates to a multi-layer display element configured by a plurality of layers for use as a display section of electronic paper or others, and a manufacturing method for the multi-layer display element. The invention provides a multi-layer display element that allows a pixel area not being narrowed, a high yield of electrode formation, and interlayer connection with no need for a high-temperature process, and a manufacturing method for such a multi-layer display element. The multi-layer liquid crystal display element includes a data signal output terminal group from which data signals are provided, a scanning signal output terminal group from which scanning signals are provided, a data electrode connection wire rod group respectively connecting data electrodes to the data signal output terminal group, and a scanning electrode connection wire rod group respectively connecting scanning electrodes to the scanning signal output terminal group.Type: GrantFiled: September 17, 2009Date of Patent: December 14, 2010Assignee: Fujitsu LimitedInventors: Hisashi Yamaguchi, Fumio Yamagishi, Shigeo Matsunuma, Nobuhiro Imaizumi, Yoshikatsu Ishizuki, Taiji Sakai, Junji Tomita
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Patent number: 7816180Abstract: The present invention realizes a semiconductor device of high reliability which allows metal terminals which have a uniform height, are flat and smooth to be formed under low load and at low costs and to be mounted with low damage. The electrodes 5 and the insulating film 6 are both formed of materials having the property that they are solid and do not exhibit the adhesiveness at room temperature and exhibit the adhesiveness at a temperature not lower than a first temperature and cure at a temperature not lower than a second temperature higher than the first temperature. The surfaces of the electrodes 5 and the insulating film 6 of a semiconductor chip 1a are planarized in continuously flat with a hard cutting tool, as of diamond or others.Type: GrantFiled: March 12, 2009Date of Patent: October 19, 2010Assignee: Fujitsu LimitedInventors: Masataka Mizukoshi, Nobuhiro Imaizumi, Yoshikatsu Ishizuki
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Patent number: 7811835Abstract: The present invention realizes a semiconductor device of high reliability which allows metal terminals which have a uniform height, are flat and smooth to be formed under low load and at low costs and to be mounted with low damage. The electrodes 5 and the insulating film 6 are both formed of materials having the property that they are solid and do not exhibit the adhesiveness at room temperature and exhibit the adhesiveness at a temperature not lower than a first temperature and cure at a temperature not lower than a second temperature higher than the first temperature. The surfaces of the electrodes 5 and the insulating film 6 of a semiconductor chip 1a are planarized in continuously flat with a hard cutting tool, as of diamond or others.Type: GrantFiled: March 12, 2009Date of Patent: October 12, 2010Assignee: Fujitsu LimitedInventors: Masataka Mizukoshi, Nobuhiro Imaizumi, Yoshikatsu Ishizuki
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Publication number: 20100097550Abstract: The invention relates to a multi-layer display element configured by a plurality of layers for use as a display section of electronic paper or others, and a manufacturing method for the multi-layer display element. The invention provides a multi-layer display element that allows a pixel area not being narrowed, a high yield of electrode formation, and interlayer connection with no need for a high-temperature process, and a manufacturing method for such a multi-layer display element. The multi-layer liquid crystal display element includes a data signal output terminal group from which data signals are provided, a scanning signal output terminal group from which scanning signals are provided, a data electrode connection wire rod group respectively connecting data electrodes to the data signal output terminal group, and a scanning electrode connection wire rod group respectively connecting scanning electrodes to the scanning signal output terminal group.Type: ApplicationFiled: September 17, 2009Publication date: April 22, 2010Applicant: FUJITSU LIMITEDInventors: Hisashi Yamaguchi, Fumio Yamagishi, Shigeo Matsunuma, Nobuhiro Imaizumi, Yoshikatsu Ishizuki, Taiji Sakai, Junji Tomita