Patents by Inventor Yoshikatsu Ishizuki
Yoshikatsu Ishizuki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7614142Abstract: A method for fabricating an interposer includes: forming on one primary surface of a first substrate a thin-film capacitor including a first capacitor electrode, a crystalline capacitor dielectric film formed on the first electrode and a second capacitor electrode formed on the dielectric film; and forming on the primary surface of the first substrate and the capacitor a first layer as semi-cured, and a first partial electrode to be a part of a through-electrode, buried in the first resin layer and electrically connected to the first electrode or the second electrode.Type: GrantFiled: February 5, 2008Date of Patent: November 10, 2009Assignee: Fujitsu LimitedInventors: Takeshi Shioga, Yoshikatsu Ishizuki, Kanae Nakagawa, Taiji Sakai, Masataka Mizukoshi, John David Baniecki, Kazuaki Kurihara
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Publication number: 20090186425Abstract: A semiconductor substrate (1) is secured by suction to a rear face (1b) of a supporting face (11a) of a substrate supporting table (11). In this event, the thickness of the semiconductor substrate (1) is made fixed by planarization on the rear face (1b), and the rear face (1b) is forcibly brought into a state free from undulation by the suction to the supporting face (11a), so that the rear face (1b) becomes a reference face for planarization of a front face (1a). In this state, a tool (10) is used to cut surface layers of Au projections (2) and a resist mask (12) on the front face (1a), thereby planarizing the Au projections (2) and the resist mask (12) so that their surfaces become continuously flat. This can planarize the surfaces of fine bumps formed on the substrate at a low cost and a high speed in place of CMP.Type: ApplicationFiled: March 30, 2009Publication date: July 23, 2009Applicant: FUJITSU LIMITEDInventors: Masataka MIZUKOSHI, Yoshikatsu ISHIZUKI, Kanae NAKAGAWA, Keishiro OKAMOTO, Kazuo TESHIROGI, Taiji SAKAI
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Publication number: 20090181497Abstract: The present invention realizes a semiconductor device of high reliability which allows metal terminals which have a uniform height, are flat and smooth to be formed under low load and at low costs and to be mounted with low damage. The electrodes 5 and the insulating film 6 are both formed of materials having the property that they are solid and do not exhibit the adhesiveness at room temperature and exhibit the adhesiveness at a temperature not lower than a first temperature and cure at a temperature not lower than a second temperature higher than the first temperature. The surfaces of the electrodes 5 and the insulating film 6 of a semiconductor chip 1a are planarized in continuously flat with a hard cutting tool, as of diamond or others.Type: ApplicationFiled: March 12, 2009Publication date: July 16, 2009Applicant: FUJITSU LIMITEDInventors: Masataka Mizukoshi, Nobuhiro Imaizumi, Yoshikatsu Ishizuki
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Publication number: 20090176331Abstract: The present invention realizes a semiconductor device of high reliability which allows metal terminals which have a uniform height, are flat and smooth to be formed under low load and at low costs and to be mounted with low damage. The electrodes 5 and the insulating film 6 are both formed of materials having the property that they are solid and do not exhibit the adhesiveness at room temperature and exhibit the adhesiveness at a temperature not lower than a first temperature and cure at a temperature not lower than a second temperature higher than the first temperature. The surfaces of the electrodes 5 and the insulating film 6 of a semiconductor chip 1a are planarized in continuously flat with a hard cutting tool, as of diamond or others.Type: ApplicationFiled: March 12, 2009Publication date: July 9, 2009Applicant: FUJITSU LIMITEDInventors: Masataka MIZUKOSHI, Nobuhiro Imaizumi, Yoshikatsu Ishizuki
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Patent number: 7514295Abstract: The present invention realizes a semiconductor device of high reliability which allows metal terminals which have a uniform height, are flat and smooth to be formed under low load and at low costs and to be mounted with low damage. The electrodes 5 and the insulating film 6 are both formed of materials having the property that they are solid and do not exhibit the adhesiveness at room temperature and exhibit the adhesiveness at a temperature not lower than a first temperature and cure at a temperature not lower than a second temperature higher than the first temperature. The surfaces of the electrodes 5 and the insulating film 6 of a semiconductor chip 1a are planarized in continuously flat with a hard cutting tool, as of diamond or others.Type: GrantFiled: August 4, 2005Date of Patent: April 7, 2009Assignee: Fujitsu LimitedInventors: Masataka Mizukoshi, Nobuhiro Imaizumi, Yoshikatsu Ishizuki
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Publication number: 20080257487Abstract: An interposer 2 comprising a base 10 formed of a plurality of resin layers 26, 34, 42, 52, 56; a thin-film capacitor 12 buried in the base 10, including a lower electrode 20, a capacitor dielectric film 22 and an upper electrode 24; a first through-electrode 14b formed through the base 10 and electrically connected to the upper electrode 24 of the thin-film capacitor 12; and a second through-electrode 14a formed through the base 10 and electrically connected to the lower electrode 20 of the thin-film capacitor 12, further comprising: an interconnection 48 buried in the base 10 and electrically connected to the respective upper electrodes 24 of a plurality of the thin-film capacitors 12, a plurality of the first through-electrodes 14b being electrically connected to the upper electrodes 24 of said plurality of the thin-film capacitors 12 via the interconnection 48, and said plurality of the first through-electrodes 14b being electrically interconnected by the interconnections 48.Type: ApplicationFiled: June 18, 2008Publication date: October 23, 2008Applicant: FUJITSU LIMITEDInventors: Takeshi Shioga, Yoshikatsu Ishizuki, John David Baniecki, Kazuaki Kurihara
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Patent number: 7405366Abstract: An interposer 2 including a base 10 formed of a plurality of resin layers 26, 34, 42, 52, 56; a thin-film capacitor 12 buried in the base 10, including a lower electrode 20, a capacitor dielectric film 22 and an upper electrode 24; a first through-electrode 14b formed through the base 10 and electrically connected to the upper electrode 24 of the thin-film capacitor 12; and a second through-electrode 14a formed through the base 10 and electrically connected to the lower electrode 20 of the thin-film capacitor 12, further including: an interconnection 48 buried in the base 10 and electrically connected to the respective upper electrodes 24 of a plurality of the thin-film capacitors 12, a plurality of the first through-electrodes 14b being electrically connected to the upper electrodes 24 of said plurality of the thin-film capacitors 12 via the interconnection 48, and said plurality of the first through-electrodes 14b being electrically interconnected by the interconnections 48.Type: GrantFiled: January 26, 2006Date of Patent: July 29, 2008Assignee: Fujitsu LimitedInventors: Takeshi Shioga, Yoshikatsu Ishizuki, John David Baniecki, Kazuaki Kurihara
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Publication number: 20080134499Abstract: The interposer comprises a base 8 formed of a plurality of resin layers 68, 20, 32, 48; thin-film capacitors 18a, 18b buried between a first resin layer 68 of said plurality of resin layers and a second resin layer 20 of said plurality of resin layers, which include first capacitor electrodes 12a, 12b, second capacitor electrodes 16 opposed to the first capacitor electrode 12a, 12b and the second capacitor electrode 16, and a capacitor dielectric film 14 of a relative dielectric constant of 200 or above formed between the first capacitor electrode 12a, 12b and the second capacitor electrode 16; a first through-electrode 77a formed through the base 8 and electrically connected to the first capacitor electrode 12a, 12b; and a second through-electrode 77b formed through the base 8 and electrically connected to the second capacitor electrode 16.Type: ApplicationFiled: February 5, 2008Publication date: June 12, 2008Applicant: FUJITSU LIMITEDInventors: Takeshi Shioga, Yoshikatsu Ishizuki, Kanae Nakagawa, Taiji Sakai, Masataka Mizukoshi, John David Baniecki, Kazuaki Kurihara
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Patent number: 7355290Abstract: The interposer comprises a base 8 formed of a plurality of resin layers 68, 20, 32, 48; thin-film capacitors 18a, 18b buried between a first resin layer 68 of said plurality of resin layers and a second resin layer 20 of said plurality of resin layers, which include first capacitor electrodes 12a, 12b, second capacitor electrodes 16 opposed to the first capacitor electrode 12a, 12b and the second capacitor electrode 16, and a capacitor dielectric film 14 of a relative dielectric constant of 200 or above formed between the first capacitor electrode 12a, 12b and the second capacitor electrode 16; a first through-electrode 77a formed through the base 8 and electrically connected to the first capacitor electrode 12a, 12b; and a second through-electrode 77b formed through the base 8 and electrically connected to the second capacitor electrode 16.Type: GrantFiled: January 25, 2006Date of Patent: April 8, 2008Assignee: Fujitsu LimitedInventors: Takeshi Shioga, Yoshikatsu Ishizuki, Kanae Nakagawa, Taiji Sakai, Masataka Mizukoshi, John David Baniecki, Kazuaki Kurihara
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Publication number: 20070090546Abstract: The interposer comprises a base 8 formed of a plurality of resin layers 68, 20, 32, 48; thin-film capacitors 18a, 18b buried between a first resin layer 68 of said plurality of resin layers and a second resin layer 20 of said plurality of resin layers, which include first capacitor electrodes 12a, 12b, second capacitor electrodes 16 opposed to the first capacitor electrode 12a, 12b and the second capacitor electrode 16, and a capacitor dielectric film 14 of a relative dielectric constant of 200 or above formed between the first capacitor electrode 12a, 12b and the second capacitor electrode 16; a first through-electrode 77a formed through the base 8 and electrically connected to the first capacitor electrode 12a, 12b; and a second through-electrode 77b formed through the base 8 and electrically connected to the second capacitor electrode 16.Type: ApplicationFiled: January 25, 2006Publication date: April 26, 2007Applicant: FUJITSU LIMITEDInventors: Takeshi Shioga, Yoshikatsu Ishizuki, Kanae Nakagawa, Taiji Sakai, Masataka Mizukoshi, John Baniecki, Kazuaki Kurihara
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Publication number: 20070076348Abstract: An interposer 2 comprising a base 10 formed of a plurality of resin layers 26, 34, 42, 52, 56; a thin-film capacitor 12 buried in the base 10, including a lower electrode 20, a capacitor dielectric film 22 and an upper electrode 24; a first through-electrode 14b formed through the base 10 and electrically connected to the upper electrode 24 of the thin-film capacitor 12; and a second through-electrode 14a formed through the base 10 and electrically connected to the lower electrode 20 of the thin-film capacitor 12, further comprising: an interconnection 48 buried in the base 10 and electrically connected to the respective upper electrodes 24 of a plurality of the thin-film capacitors 12, a plurality of the first through-electrodes 14b being electrically connected to the upper electrodes 24 of said plurality of the thin-film capacitors 12 via the interconnection 48, and said plurality of the first through-electrodes 14b being electrically interconnected by the interconnections 48.Type: ApplicationFiled: January 26, 2006Publication date: April 5, 2007Applicant: FUJITSU LIMITEDInventors: Takeshi Shioga, Yoshikatsu Ishizuki, John Baniecki, Kazuaki Kurihara
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Publication number: 20060030071Abstract: The present invention realizes a semiconductor device of high reliability which allows metal terminals which have a uniform height, are flat and smooth to be formed under low load and at low costs and to be mounted with low damage. The electrodes 5 and the insulating film 6 are both formed of materials having the property that they are solid and do not exhibit the adhesiveness at room temperature and exhibit the adhesiveness at a temperature not lower than a first temperature and cure at a temperature not lower than a second temperature higher than the first temperature. The surfaces of the electrodes 5 and the insulating film 6 of a semiconductor chip 1a are planarized in continuously flat with a hard cutting tool, as of diamond or others.Type: ApplicationFiled: August 4, 2005Publication date: February 9, 2006Applicant: FUJITSU LIMITEDInventors: Masataka Mizukoshi, Nobuhiro Imaizumi, Yoshikatsu Ishizuki
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Publication number: 20060027936Abstract: Electrodes and an insulating film are both formed of materials which have characteristics that they are solid and do not exhibit adhesiveness at a room temperature, exhibit adhesiveness at and above a first temperature higher than this, and are cured at and above a second temperature higher than this. Planarication processing is carried out by performing cutting with a hard cutting tool made of diamond and the like so that surfaces film the electrodes and a surface of the insulating film become continuously planar.Type: ApplicationFiled: December 22, 2004Publication date: February 9, 2006Applicant: FUJITSU LIMITEDInventors: Masataka Mizukoshi, Nobuhiro Imaizumi, Yoshikatsu Ishizuki
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Patent number: 6943447Abstract: A thin film multi-layer wiring substrate comprising a plurality of wiring layers, each adjacent pair of wiring layers being separated by an insulating layer, wherein at least one of the wiring layers includes wiring formed by an inner conductor member and a conductor layer surrounding the periphery thereof through an insulating material.Type: GrantFiled: January 9, 2003Date of Patent: September 13, 2005Assignee: Fujitsu LimitedInventors: Yoshikatsu Ishizuki, Nobuyuki Hayashi, Masataka Mizukoshi, Yasuo Yamagishi
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Publication number: 20050161814Abstract: A semiconductor substrate (1) is secured by suction to a rear face (1b) of a supporting face (11a) of a substrate supporting table (11). In this event, the thickness of the semiconductor substrate (1) is made fixed by planarization on the rear face (1b), and the rear face (1b) is forcibly brought into a state free from undulation by the suction to the supporting face (11a), so that the rear face (1b) becomes a reference face for planarization of a front face (1a). In this state, a tool (10) is used to cut surface layers of Au projections (2) and a resist mask (12) on the front face (1a), thereby planarizing the Au projections (2) and the resist mask (12) so that their surfaces become continuously flat. This can planarize the surfaces of fine bumps formed on the substrate at a low cost and a high speed in place of CMP.Type: ApplicationFiled: March 21, 2005Publication date: July 28, 2005Applicant: FUJITSU LIMITEDInventors: Masataka Mizukoshi, Yoshikatsu Ishizuki, Kanae Nakagawa, Keishiro Okamoto, Kazuo Teshirogi, Taiji Sakai
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Publication number: 20050109533Abstract: A manufacturing method of a circuit board includes the steps of: forming projecting electrodes on a substrate; forming a photosensitive resin film on the substrate so as to cover the projecting electrodes; exposing a substantially entire surface of the photosensitive film; and melting the surface of the photosensitive film so as to expose the projecting electrodes.Type: ApplicationFiled: December 28, 2004Publication date: May 26, 2005Applicant: FUJITSU LIMITEDInventors: Mamoru Kurashina, Yoshikatsu Ishizuki, Nawalage Cooray, Masataka Mizukoshi
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Publication number: 20040009666Abstract: A thin film multi-layer wiring substrate comprising a plurality of wiring layers, each adjacent pair of wiring layers being separated by an insulating layer, wherein at least one of the wiring layers includes wiring formed by an inner conductor member and a conductor layer surrounding the periphery thereof through an insulating material. A printed circuit board comprising a signal line conductor formed on a first insulating layer which selectively covers a first ground layer spreading on a substrate, shield walls extending across gaps on both sides of the signal line conductor, and conductively connected to the first ground layer, and a second ground layer conductively connected to the shield walls, stretching across gaps above the signal line conductor, and in which a plurality of openings having lengths and distances of equal to or less than one quarter of a frequency handled by the signal line conductor are formed, is also disclosed.Type: ApplicationFiled: January 9, 2003Publication date: January 15, 2004Applicant: FUJITSU LIMITEDInventors: Yoshikatsu Ishizuki, Nobuyuki Hayashi, Masataka Mizukoshi, Yasuo Yamagishi
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Patent number: 6001488Abstract: A resin composition comprising an epoxy group-containing cycloolefin resin and a crosslinking agent is provided. More specifically, a resin composition comprising an epoxy group-containing thermoplastic norbornene resin obtained by introducing epoxy groups into a thermoplastic norbornene resin, and as the crosslinking agent, a curing agent for epoxy resins or a photoreactive substance is provided. The resin composition is suitable for use as an insulating material.Type: GrantFiled: June 29, 1998Date of Patent: December 14, 1999Assignees: Nippon Zeon Co., Ltd., Fujitsu LimitedInventors: Hideaki Kataoka, Eiko Yuda, Shigemitsu Kamiya, Masahide Yamamoto, Yoshikatsu Ishizuki, Yasuhiro Yoneda, Daisuke Mizutani, Kishio Yokouchi
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Patent number: 5895800Abstract: A resin composition comprising an epoxy group-containing cycloolefin resin and a crosslinking agent is provided. More specifically, a resin composition comprising an epoxy group-containing thermoplastic norbornene resin obtained by introducing epoxy groups into a thermoplastic norbornene resin, and as the crosslinking agent, a curing agent for epoxy resins or a photoreactive substance is provided. The resin composition is suitable for use as an insulating material.Type: GrantFiled: June 29, 1998Date of Patent: April 20, 1999Assignees: Nippon Zeon Co., Ltd., Fujitsu LimitedInventors: Hideaki Kataoka, Eiko Yuda, Shigemitsu Kamiya, Masahide Yamamoto, Yoshikatsu Ishizuki, Yasuhiro Yoneda, Daisuke Mizutani, Kishio Yokouchi
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Patent number: 5886136Abstract: Disclosed herein is a pattern forming process comprising the steps of coating a substrate with a photosensitive resin composition comprising a polyamic compound having, at each terminal thereof, an actinic ray-sensitive functional group which has substituent groups each having a photopolymerizable carbon-carbon double bond, a photosensitive auxiliary having a photopolymerizable functional group, a photopolymerization initiator, and a solvent to form a film; subjecting the film to pattering exposure; and then developing the thus-exposed film with an alkaline developer or alkaline aqueous solution.Type: GrantFiled: March 17, 1997Date of Patent: March 23, 1999Assignees: Nippon Zeon Co., Ltd., Fujitsu LimitedInventors: Akira Tanaka, Masami Koshiyama, Kei Sakamoto, Yasuhiro Yoneda, Kishio Yokouchi, Daisuke Mizutani, Yoshikatsu Ishizuki