Patents by Inventor Yoshinori Kumura
Yoshinori Kumura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20090095993Abstract: According to an aspect of the present invention, there is provided a semiconductor memory device including a ferroelectric capacitor, including a semiconductor substrate, a transistor having diffusion layers being a source and a drain, the transistor being formed on a surface of the semiconductor substrate, a ferroelectric capacitor being formed over the transistor, the ferroelectric capacitor including a lower electrode, a ferroelectric film and an upper electrode stacked in order, an interlayer insulator separating between the transistor and the ferroelectric capacitor, a first contact plug being embedded in the interlayer insulator formed beneath the ferroelectric capacitor, the first contact plug directly connecting between one of the diffusion layers and the lower electrode, a first hydrogen barrier film covering the transistor a second hydrogen barrier film, a portion of the second hydrogen barrier film being formed on the first hydrogen barrier film, another portion of the second hydrogen barrier filmType: ApplicationFiled: October 2, 2008Publication date: April 16, 2009Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Tohru Ozaki, Yoshinori Kumura
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Publication number: 20090095994Abstract: A semiconductor device comprises a substrate; an insulating layer formed over the substrate; a contact hole formed through the insulating layer; a plurality of first plug electrodes each formed inside the contact hole to the surface of the insulating layer; a capacitor layer formed on the first plug electrode in a first region; and a second plug electrode formed on the first plug electrode in a second region different from the first region. The capacitor layer includes a lower electrode, a ferroelectric film, and an upper electrode stacked in turn. The first plug electrode includes a plug conduction layer formed from the surface of the substrate, and a plug barrier layer formed from above the plug conduction layer up to an upper surface of the insulating layer, the plug barrier layer having a higher etching selection ratio than the lower electrode.Type: ApplicationFiled: October 14, 2008Publication date: April 16, 2009Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Hiroyuki Kanaya, Yoshinori Kumura
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Publication number: 20090078979Abstract: A semiconductor device includes: a semiconductor substrate and a transistor formed on the semiconductor substrate. The semiconductor device also includes: a first interlayer insulation film formed on the semiconductor substrate including the upper portion of the transistor, a first contact formed to be connected through the first interlayer insulation film to the transistor, a ferroelectric capacitor formed to be connected to the first contact, a second interlayer insulation film formed on the first interlayer insulation film, and a second contact formed to connect the ferroelectric capacitor to a wiring through the second interlayer insulation film. The contact surfaces between the second contact and the ferroelectric capacitor have the same planar shape.Type: ApplicationFiled: September 19, 2008Publication date: March 26, 2009Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yoshinori KUMURA, Yoshiro SHIMOJO
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Patent number: 7504680Abstract: A semiconductor device according to an aspect of the invention includes a semiconductor substrate, and a capacitor that is provided above the semiconductor substrate and is configured such that a dielectric film is sandwiched between a lower electrode and an upper electrode, the dielectric film being formed of an ABO3 perovskite-type oxide that includes at least one of Pb, Ba and Sr as an A-site element and at least one of Zr, Ti, Ta, Nb, Mg, W, Fe and Co as a B-site element, wherein a radius of curvature of a sidewall of the capacitor, when viewed from above or in a film thickness direction, is 250 [nm] or less, and a length of an arc with the radius of curvature is {250 [nm]×?/6 [rad]} or less.Type: GrantFiled: April 18, 2005Date of Patent: March 17, 2009Assignees: Kabushiki Kaisha Toshiba, Infineon Technologies AGInventors: Osamu Arisumi, Yoshinori Kumura, Kazuhiro Tomioka, Ulrich Egger, Haoran Zhuang, Bum-ki Moon
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Publication number: 20080308902Abstract: This disclosure concerns a semiconductor device comprising a switching transistor provided on a semiconductor substrate; an interlayer dielectric film formed on the switching transistor; a ferroelectric capacitor including an upper electrode, a ferroelectric film, and a lower electrode formed on the interlayer dielectric film; a contact plug provided in the interlayer dielectric film and electrically connected to the lower electrode; a diffusion layer connecting between the contact plug and the switching transistor; a trench formed around the ferroelectric capacitor; and a barrier film filling in the trench and provided on a side surface of the ferroelectric capacitor and on an upper surface of the interlayer dielectric film, the barrier film suppressing percolation of hydrogen, wherein a thickness of the barrier film on the side surface of the ferroelectric capacitor is larger than a thickness of the barrier film on the upper surface of the interlayer dielectric film.Type: ApplicationFiled: May 22, 2008Publication date: December 18, 2008Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yoshinori KUMURA, Tohru Ozaki
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Publication number: 20080230818Abstract: According to an aspect of the present invention, there is provided a non-volatile memory including: a transistor formed on a semiconductor substrate, the transistor including: two diffusion layers and a gate therebetween; a first insulating film formed on a top and a side surfaces of the gate; a first and a second contact plugs formed on corresponding one of the diffusion layers to contact the first insulating film; a ferroelectric capacitor formed on the first contact plug and on the first insulating film, the ferroelectric capacitor including: a first and a second electrodes and a ferroelectric film therebetween; a third contact plug formed on the second electrode; and a fourth contact plug formed on the second contact plug.Type: ApplicationFiled: March 21, 2008Publication date: September 25, 2008Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yoshinori Kumura, Tohru Ozaki, Iwao Kunishima
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Patent number: 7417274Abstract: A semiconductor device comprises an insulation film that is provided on a semiconductor substrate, a first contact plug that is provided in the insulation film and includes a metal, a first adhesive film that is provided on the insulation film, has a higher oxygen affinity than the metal, and includes an oxide, a second adhesive film that is provided on the first contact plug and has a film thickness that is smaller than a film thickness of the first adhesive film, a first capacitor electrode that is provided on the contact plug and the first adhesive film, has a part in direct contact with the first contact plug, a capacitor insulation film that is provided on the first capacitor electrode, and a second capacitor electrode that is provided on the capacitor insulation film.Type: GrantFiled: July 25, 2006Date of Patent: August 26, 2008Assignee: Kabushiki Kaisha ToshibaInventors: Tohru Ozaki, Yoshinori Kumura, Yoshiro Shimojo, Susumu Shuto
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Publication number: 20080173912Abstract: A semiconductor device comprising a ferroelectric capacitor having improved reliability is disclosed. According to one aspect of the present invention, it is provided a semiconductor device comprising a transistor formed on a semiconductor substrate, a ferroelectric capacitor formed above the transistor and comprising a lower electrode, a ferroelectric film and an upper electrode, a first hydrogen barrier film formed over the ferroelectric capacitor, an insulator formed over the first hydrogen barrier film, a contact plug disposed in the insulator and electrically connected with the upper electrode, a second hydrogen barrier film disposed between the contact plug and the insulator continuously, and a wiring connected with the contact plug.Type: ApplicationFiled: November 16, 2007Publication date: July 24, 2008Inventors: Yoshinori KUMURA, Tohru Ozaki, Susumu Shuto, Yoshiro Shimojo, Iwao Kunishima
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Patent number: 7400005Abstract: A semiconductor memory device, which prevents the penetration of hydrogen or moisture to a ferroelectric capacitor from its surrounding area including a contact plug portion, comprises a ferroelectric capacitor formed above a semiconductor substrate, a first hydrogen barrier film formed on an upper surface of the ferroelectric capacitor to work as a mask in the formation of the ferroelectric capacitor, a second hydrogen barrier film formed on the upper surface and a side face of the ferroelectric capacitor including on the first hydrogen barrier film, and a contact plug disposed through the first and second hydrogen barrier films, and connected to an upper electrode of the ferroelectric capacitor, a side face thereof being surrounded with the hydrogen barrier films.Type: GrantFiled: June 2, 2005Date of Patent: July 15, 2008Assignee: Kabushiki Kaisha ToshibaInventors: Yoshinori Kumura, Iwao Kunishima, Hiroyuki Kanaya, Tohru Ozaki, Kazuhiro Tomioka
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Publication number: 20080073682Abstract: According to an aspect of the present invention, there is provided a non-volatile semiconductor memory device, including a ferroelectric capacitor being stacked a first electrode, a ferroelectric film and a second electrode in order, a first protective film with hydrogen barrier performance, the first protective film being formed under the first electrode and on a side-wall of the ferroelectric capacitor, the first protective film being widened from the second electrode towards the first electrode, a second protective film with hydrogen barrier performance, the second protective film being formed over the second electrode and on the first protective film formed on the side-wall of the ferroelectric capacitor, the second protective film being widened from the first electrode towards the second electrode, a cell transistor, a source of the cell transistor being connected to the first electrode, a drain of the cell transistor being connected to a bit line and a gate being connected to a word line.Type: ApplicationFiled: September 18, 2007Publication date: March 27, 2008Inventors: Yoshinori Kumura, Tohru Ozaki, Iwao Kunishima
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Patent number: 7348617Abstract: A semiconductor device comprising a ferroelectric capacitor having improved reliability is disclosed. According to one aspect of the present invention, it is provided a semiconductor device comprising a transistor formed on a semiconductor substrate, a ferroelectric capacitor formed above the transistor and comprising a lower electrode, a ferroelectric film and an upper electrode, a first hydrogen barrier film formed over the ferroelectric capacitor, an insulator formed over the first hydrogen barrier film, a contact plug disposed in the insulator and electrically connected with the upper electrode, a second hydrogen barrier film disposed between the contact plug and the insulator continuously, and a wiring connected with the contact plug.Type: GrantFiled: November 29, 2005Date of Patent: March 25, 2008Assignee: Kabushiki Kaisha ToshibaInventors: Yoshinori Kumura, Tohru Ozaki, Susumu Shuto, Yoshiro Shimojo, Iwao Kunishima
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Publication number: 20080061335Abstract: According to an aspect of the present invention, there is provided a semiconductor memory including a lower electrode, a first insulating region formed in the same layer as the lower electrode, a ferroelectric film formed on the lower electrode and on the first insulating region, an upper electrode formed on the ferroelectric film, a second insulating region formed in the same layer as the upper electrode and a transistor. The first insulating region partitions the lower electrode. The second insulating region partitions the upper electrode. The transistor includes a first impurity region connected to the lower electrode and a second impurity region connected to the upper electrode. At least one of the first insulating region and the second insulating region is formed by insulating the lower electrode or the upper electrode.Type: ApplicationFiled: September 11, 2007Publication date: March 13, 2008Inventors: Yoshinori Kumura, Tohru Ozaki, Iwao Kunishima
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Patent number: 7259094Abstract: An apparatus for manufacturing a semiconductor device is disclosed which comprises a chamber which holds a to-be-processed substrate having a film containing at least one kind of metal element which will become a component of a volatile metal compound, a heater which heats the substrate held in the chamber, and an adsorbent which is provided in the chamber and which adsorbs the volatile metal compound generated from the film by heating the substrate.Type: GrantFiled: April 21, 2005Date of Patent: August 21, 2007Assignee: Kabushiki Kaisha ToshibaInventors: Katsuaki Natori, Keisuke Nakazawa, Koji Yamakawa, Hiroyuki Kanaya, Yoshinori Kumura, Hiroshi Itokawa, Osamu Arisumi
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Patent number: 7214982Abstract: A semiconductor device including a ferroelectric random access memory, which has a structure suitable for miniaturization and easy to manufacture, and having less restrictions on materials to be used, comprises a field effect transistor formed on a surface area of a semiconductor wafer, a trench ferroelectric capacitor formed in the semiconductor wafer in one source/drain of the field effect transistor, wherein one electrode thereof is connected to the source/drain, and a wiring formed in the semiconductor wafer and connected to the other electrode of the trench ferroelectric capacitor.Type: GrantFiled: October 7, 2004Date of Patent: May 8, 2007Assignee: Kabushiki Kaisha ToshibaInventors: Yoshinori Kumura, Iwao Kunishima, Tohru Ozaki
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Publication number: 20070072310Abstract: A semiconductor device comprising a semiconductor substrate and memory cells. Each memory cell comprises a switching transistor and a ferroelectric capacitor, both formed on the substrate. The ferroelectric capacitor includes a lower electrode, an upper electrode and a ferroelectric film held between the lower and upper electrodes. A first wire formed from a deposited wire-material film is connected to the upper electrode of the ferroelectric capacitor. A second wire formed by damascene process is provided on the first wire.Type: ApplicationFiled: March 1, 2006Publication date: March 29, 2007Inventors: Yoshinori Kumura, Tohru Ozaki, Susumu Shuto
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Publication number: 20070054462Abstract: A semiconductor device comprises an insulation film that is provided on a semiconductor substrate, a first contact plug that is provided in the insulation film and includes a metal, a first adhesive film that is provided on the insulation film, has a higher oxygen affinity than the metal, and includes an oxide, a second adhesive film that is provided on the first contact plug and has a film thickness that is smaller than a film thickness of the first adhesive film, a first capacitor electrode that is provided on the contact plug and the first adhesive film, has a part in direct contact with the first contact plug, a capacitor insulation film that is provided on the first capacitor electrode, and a second capacitor electrode that is provided on the capacitor insulation film.Type: ApplicationFiled: July 25, 2006Publication date: March 8, 2007Inventors: Tohru Ozaki, Yoshinori Kumura, Yoshiro Shimojo, Susumu Shuto
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Publication number: 20070045687Abstract: A semiconductor device comprising a ferroelectric capacitor having improved reliability is disclosed. According to one aspect of the present invention, it is provided a semiconductor device comprising a transistor formed on a semiconductor substrate, a ferroelectric capacitor formed above the transistor and comprising a lower electrode, a ferroelectric film and an upper electrode, a first hydrogen barrier film formed over the ferroelectric capacitor, an insulator formed over the first hydrogen barrier film, a contact plug disposed in the insulator and electrically connected with the upper electrode, a second hydrogen barrier film disposed between the contact plug and the insulator continuously, and a wiring connected with the contact plug.Type: ApplicationFiled: November 29, 2005Publication date: March 1, 2007Inventors: Yoshinori Kumura, Tohru Ozaki, Susumu Shuto, Yoshiro Shimojo, Iwao Kunishima
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Publication number: 20060231876Abstract: A semiconductor device according to an aspect of the invention comprises a semiconductor substrate, and a capacitor that is provided above the semiconductor substrate and is configured such that a dielectric film is sandwiched between a lower electrode and an upper electrode, the dielectric film being formed of an ABO3 perovskite-type oxide that includes at least one of Pb, Ba and Sr as an A-site element and at least one of Zr, Ti, Ta, Nb, Mg, W, Fe and Co as a B-site element, wherein a radius of curvature of a side wall of the capacitor, when viewed from above or in a film thickness direction, is 250 [nm] or less, and a length of an arc with the radius of curvature is {250 [nm]×?/6 [rad]} or more.Type: ApplicationFiled: April 18, 2005Publication date: October 19, 2006Inventors: Osamu Arisumi, Yoshinori Kumura, Kazuhiro Tomioka, Ulrich Egger, Haoran Zhuang, Bum-ki Moon
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Patent number: 7095068Abstract: A semiconductor memory device includes a semiconductor substrate, a first transistor formed on the semiconductor substrate and including a first gate electrode and first and second diffusion layers, a first contact connected to the first diffusion layer, a first conductive oxygen barrier film electrically connected to the first contact and covering at least the upper surface of the first contact, a first ferroelectric capacitor including a first electrode, a second electrode, and a first ferroelectric film interposed between the first and second electrodes, and a first connecting member connected to the first electrode and to the first conductive oxygen barrier film.Type: GrantFiled: June 6, 2003Date of Patent: August 22, 2006Assignee: Kabushiki Kaisha ToshibaInventors: Yoshinori Kumura, Iwao Kunishima, Tohru Ozaki, Hiroyuki Kanaya, Shinichi Watanabe
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Publication number: 20060180894Abstract: A semiconductor memory device, which prevents the penetration of hydrogen or moisture to a ferroelectric capacitor from its surrounding area including a contact plug portion, comprises a ferroelectric capacitor formed above a semiconductor substrate, a first hydrogen barrier film formed on an upper surface of the ferroelectric capacitor to work as a mask in the formation of the ferroelectric capacitor, a second hydrogen barrier film formed on the upper surface and a side face of the ferroelectric capacitor including on the first hydrogen barrier film, and a contact plug disposed through the first and second hydrogen barrier films, and connected to an upper electrode of the ferroelectric capacitor, a side face thereof being surrounded with the hydrogen barrier films.Type: ApplicationFiled: June 2, 2005Publication date: August 17, 2006Inventors: Yoshinori Kumura, Iwao Kunishima, Hiroyuki Kanaya, Tohru Ozaki, Kazuhiro Tomioka