Patents by Inventor Yoshinori Kumura

Yoshinori Kumura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040084701
    Abstract: A semiconductor device having a semiconductor substrate; an insulating film formed on said semiconductor substrate; a ferroelectric capacitor having a lower electrode, a ferroelectric film and an upper electrode which are stacked sequentially on the insulating film; a first hydrogen barrier film; a first inter-layer insulating film covering said ferroelectric capacitor; and a second inter-layer insulating film stacked on the first inter-layer insulating film, the first hydrogen barrier film being interposed between the first and second interlayer insulating films is proposed.
    Type: Application
    Filed: June 25, 2003
    Publication date: May 6, 2004
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hiroyuki Kanaya, Toyota Morimoto, Osamu Hidaka, Yoshinori Kumura, Iwao Kunishima, Tsuyoshi Iwamoto
  • Publication number: 20040056290
    Abstract: There is provided a semiconductor device having a ferroelectric capacitor formed on a semiconductor substrate covered with an insulator film, wherein the ferroelectric capacitor comprises: a bottom electrode formed on the insulator film; a ferroelectric film formed on the bottom electrode; and a top electrode formed on the ferroelectric film. The ferroelectric film has a stacked structure of either of two-layer-ferroelectric film or three-layer-ferroelectric film. The upper ferroelectric film is metallized and prevents hydrogen from diffusing in lower ferroelectric layer. Crystal grains of the stacked ferroelectric films are preferably different.
    Type: Application
    Filed: May 22, 2003
    Publication date: March 25, 2004
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hiroyuki Kanaya, Iwao Kunishima, Koji Yamakawa, Tsuyoshi Iwamoto, Hiroshi Mochizuki, Yoshinori Kumura
  • Patent number: 6680499
    Abstract: Provided are a semiconductor memory device that permits increasing the degree of integration without decreasing the capacitance of the capacitor included in a memory cell, and a method of manufacturing the particular semiconductor memory device. Specifically, provided are a semiconductor memory device, comprising a semiconductor substrate, an interlayer insulating film formed on the semiconductor substrate, a first electrode formed on the interlayer insulating film, a first ferroelectric film formed on the first electrode, a second electrode formed on the first ferroelectric film, a second ferroelectric film formed on the second electrode, and a third electrode formed on the second ferroelectric film, and a method of manufacturing the particular semiconductor memory device.
    Type: Grant
    Filed: November 19, 2001
    Date of Patent: January 20, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshinori Kumura, Hiroyuki Kanaya, Iwao Kunishima
  • Publication number: 20030205738
    Abstract: A lower electrode is formed on an insulating film on a semiconductor substrate. A pair of ferroelectric films are formed on the lower electrode separately from each other. An upper electrode is formed on each of the pair of ferroelectric films. A portion of the lower electrode on which the ferroelectric film is formed is thicker than a portion thereof on which the ferroelectric film is not formed. Such a structure is obtained by sequentially depositing the lower electrode, the ferroelectric film, and the upper electrode on the insulating film, forming a mask on the upper-electrode, using this mask to etch the upper-electrode and the ferroelectric film to thereby pattern a pair of upper electrodes and a pair of ferroelectric electrodes, forming such a mask that continuously covers the pair of upper electrodes and the pair of ferroelectric films, and then etching the lower-electrode material film.
    Type: Application
    Filed: May 30, 2003
    Publication date: November 6, 2003
    Inventors: Hiroyuki Kanaya, Yasuyuki Taniguchi, Tohru Ozaki, Yoshinori Kumura
  • Patent number: 6611014
    Abstract: A semiconductor device having a semiconductor substrate; an insulating film formed on said semiconductor substrate; a ferroelectric capacitor having a lower electrode, a ferroelectric film and an upper electrode which are stacked sequentially on the insulating film; a first hydrogen barrier film; a first inter-layer insulating film covering said ferroelectric capacitor; and a second inter-layer insulating film stacked on the first inter-layer insulating film, the first hydrogen barrier film being interposed between the first and second interlayer insulating films is proposed.
    Type: Grant
    Filed: May 12, 2000
    Date of Patent: August 26, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroyuki Kanaya, Toyota Morimoto, Osamu Hidaka, Yoshinori Kumura, Iwao Kunishima, Tsuyoshi Iwamoto
  • Patent number: 6603161
    Abstract: There is provided a semiconductor device having a ferroelectric capacitor formed on a semiconductor substrate covered with an insulator film, wherein the ferroelectric capacitor comprises: a bottom electrode formed on the insulator film; a ferroelectric film formed on the bottom electrode; and a top electrode formed on the ferroelectric film. The ferroelectric film has a stacked structure of either of two-layer-ferroelectric film or three-layer-ferroelectric film. The upper ferroelectric film is metallized and prevents hydrogen from diffusing in lower ferroelectric layer. Crystal grains of the stacked ferroelectric films are preferably different.
    Type: Grant
    Filed: March 9, 2001
    Date of Patent: August 5, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroyuki Kanaya, Yasuyuki Taniguchi, Tohru Ozaki, Yoshinori Kumura
  • Publication number: 20020075736
    Abstract: Provided are a semiconductor memory device that permits increasing the degree of integration without decreasing the capacitance of the capacitor included in a memory cell, and a method of manufacturing the particular semiconductor memory device. Specifically, provided are a semiconductor memory device, comprising a semiconductor substrate, an interlayer insulating film formed on the semiconductor substrate, a first electrode formed on the interlayer insulating film, a first ferroelectric film formed on the first electrode, a second electrode formed on the first ferroelectric film, a second ferroelectric film formed on the second electrode, and a third electrode formed on the second ferroelectric film, and a method of manufacturing the particular semiconductor memory device.
    Type: Application
    Filed: November 19, 2001
    Publication date: June 20, 2002
    Inventors: Yoshinori Kumura, Hiroyuki Kanaya, Iwao Kunishima
  • Publication number: 20010022372
    Abstract: There is provided a semiconductor device having a ferroelectric capacitor formed on a semiconductor substrate covered with an insulator film, wherein the ferroelectric capacitor comprises: a bottom electrode formed on the insulator film; a ferroelectric film formed on the bottom electrode; and a top electrode formed on the ferroelectric film. The ferroelectric film has a stacked structure of either of two-layer-ferroelectric film or three-layer-ferroelectric film. The upper ferroelectric film is metallized and prevents hydrogen from diffusing in lower ferroelectric layer. Crystal grains of the stacked ferroelectric films are preferably different.
    Type: Application
    Filed: March 9, 2001
    Publication date: September 20, 2001
    Inventors: Hiroyuki Kanaya, Yasuyuki Taniguchi, Tohru Ozaki, Yoshinori Kumura