Patents by Inventor Yoshiro Shimojo
Yoshiro Shimojo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230114433Abstract: According to one embodiment, a stacked body includes a plurality of electrode layers stacked with an insulator interposed. A conductive via pierces the stacked body, and connects an upper layer interconnect and a lower layer interconnect. A insulating film is provided between the via and the stacked body. A distance along a diametral direction of the via between a side surface of the via and an end surface of one of the electrode layers opposing the side surface of the via is greater than a distance along the diametral direction between the side surface of the via and an end surface of the insulator opposing the side surface of the via.Type: ApplicationFiled: December 12, 2022Publication date: April 13, 2023Applicant: Kioxia CorporationInventors: Yasuhito YOSHIMIZU, Yoshiro Shimojo, Shinya Arai
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Patent number: 11552000Abstract: According to one embodiment, a stacked body includes a plurality of electrode layers stacked with an insulator interposed. A conductive via pierces the stacked body, and connects an upper layer interconnect and a lower layer interconnect. A insulating film is provided between the via and the stacked body. A distance along a diametral direction of the via between a side surface of the via and an end surface of one of the electrode layers opposing the side surface of the via is greater than a distance along the diametral direction between the side surface of the via and an end surface of the insulator opposing the side surface of the via.Type: GrantFiled: October 26, 2020Date of Patent: January 10, 2023Assignee: Kioxia CorporationInventors: Yasuhito Yoshimizu, Yoshiro Shimojo, Shinya Arai
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Publication number: 20220285391Abstract: In a method for manufacturing a memory, a first stacked body is formed by stacking a first insulating film and a first sacrificial film. A first columnar body including a first semiconductor portion extending in the first stacked body in the first direction and a charge trapping film provided on an outer peripheral surface of the first semiconductor portion is formed. A second columnar body provided in a second direction of the first columnar body and including a second semiconductor portion stretching in the first stacked body in the first direction and a charge trapping film on an outer peripheral surface of the second semiconductor portion is formed. A second insulating film is formed above the first stacked body.Type: ApplicationFiled: August 26, 2021Publication date: September 8, 2022Applicant: Kioxia CorporationInventors: Kazuharu YAMABE, Yoshiro SHIMOJO
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Publication number: 20220278215Abstract: A semiconductor storage device includes a first stacked body including first insulating films and first conductive films that are alternately stacked in a first direction. A first columnar body and a second columnar body extend within the first stacked body in the first direction. A second conductive film is provided above the first stacked body, and extends in a third direction intersecting the first direction and the second direction. A third insulator is adjacent to the second conductive film and extends in the third direction. A third conductive film is adjacent to the third insulator and extends in the third direction. A third columnar body is provided on the first columnar body. A fourth columnar body is provided on the second columnar body. A thickness of a third semiconductor portion in the first direction is greater than a thickness of the second conductive film in the first direction.Type: ApplicationFiled: August 23, 2021Publication date: September 1, 2022Inventor: Yoshiro SHIMOJO
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Patent number: 11222900Abstract: According to one embodiment, a semiconductor memory device includes: a first interconnect layer including a first electrode that extends in a first direction and a second electrode that extends in a second direction and is in contact with one end of the first electrode; a second interconnect layer including a third electrode that is provided adjacently to the first electrode and a fourth electrode that is in contact with one end of the third electrode; a first semiconductor layer provided between the first electrode and the third electrode; a first charge storage layer provided between the first semiconductor layer and the first electrode; a second charge storage layer provided between the first semiconductor layer and the third electrode; and a first bit line provided above the first semiconductor layer and extending in the first direction.Type: GrantFiled: December 21, 2018Date of Patent: January 11, 2022Assignee: Toshiba Memory CorporationInventors: Yoshiro Shimojo, Tomoya Sanuki
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Publication number: 20210399004Abstract: A semiconductor storage device includes a first conductive layer, a second conductive layer, a third conductive layer, a contact plug, a memory trench extending between the second conductive layer and the third conductive layer. The memory trench is formed around the contact plug, and surrounds a first area in which the contact plug is disposed. A second area is separated from the first area and includes a pillar penetrating the first conductive layer. The second conductive layer extends between the first and second areas, and is connected to the first conductive layer. The third conductive layer is on the opposite side of the first area to the second area, and is connected to the first conductive layer.Type: ApplicationFiled: August 31, 2021Publication date: December 23, 2021Applicant: TOSHIBA MEMORY CORPORATIONInventors: Keisuke NAKATSUKA, Yoshitaka KUBOTA, Tetsuaki UTSUMI, Yoshiro SHIMOJO, Ryota KATSUMATA
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Patent number: 11121147Abstract: A semiconductor storage device includes a first conductive layer, a second conductive layer, a third conductive layer, a contact plug, a memory trench extending between the second conductive layer and the third conductive layer. The memory trench is formed around the contact plug, and surrounds a first area in which the contact plug is disposed. A second area is separated from the first area and includes a pillar penetrating the first conductive layer. The second conductive layer extends between the first and second areas, and is connected to the first conductive layer. The third conductive layer is on the opposite side of the first area to the second area, and is connected to the first conductive layer.Type: GrantFiled: September 3, 2019Date of Patent: September 14, 2021Assignee: TOSHIBA MEMORY CORPORATIONInventors: Keisuke Nakatsuka, Yoshitaka Kubota, Tetsuaki Utsumi, Yoshiro Shimojo, Ryota Katsumata
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Publication number: 20210159237Abstract: According to one embodiment, a semiconductor memory device includes: a substrate; a first interconnect; a second interconnect; a plurality of third interconnects; a fourth interconnect; a semiconductor member; a charge storage member; and a conductive member. One of the plurality of third interconnects is disposed on two second-direction sides of the conductive member. Portions of the one of the plurality of third interconnects disposed on the two second-direction sides of the conductive member are formed as one body.Type: ApplicationFiled: February 2, 2021Publication date: May 27, 2021Applicant: TOSHIBA MEMORY CORPORATIONInventor: Yoshiro SHIMOJO
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Patent number: 10943914Abstract: According to one embodiment, a semiconductor memory device includes: a substrate; a first interconnect; a second interconnect; a plurality of third interconnects; a fourth interconnect; a semiconductor member; a charge storage member; and a conductive member. One of the plurality of third interconnects is disposed on two second-direction sides of the conductive member. Portions of the one of the plurality of third interconnects disposed on the two second-direction sides of the conductive member are formed as one body.Type: GrantFiled: May 14, 2020Date of Patent: March 9, 2021Assignee: TOSHIBA MEMORY CORPORATIONInventor: Yoshiro Shimojo
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Publication number: 20210043546Abstract: According to one embodiment, a stacked body includes a plurality of electrode layers stacked with an insulator interposed. A conductive via pierces the stacked body, and connects an upper layer interconnect and a lower layer interconnect. A insulating film is provided between the via and the stacked body. A distance along a diametral direction of the via between a side surface of the via and an end surface of one of the electrode layers opposing the side surface of the via is greater than a distance along the diametral direction between the side surface of the via and an end surface of the insulator opposing the side surface of the via.Type: ApplicationFiled: October 26, 2020Publication date: February 11, 2021Applicant: Toshiba Memory CorporationInventors: Yasuhito YOSHIMIZU, Yoshiro SHIMOJO, Shinya ARAI
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Patent number: 10854534Abstract: According to one embodiment, a stacked body includes a plurality of electrode layers stacked with an insulator interposed. A conductive via pierces the stacked body, and connects an upper layer interconnect and a lower layer interconnect. A insulating film is provided between the via and the stacked body. A distance along a diametral direction of the via between a side surface of the via and an end surface of one of the electrode layers opposing the side surface of the via is greater than a distance along the diametral direction between the side surface of the via and an end surface of the insulator opposing the side surface of the via.Type: GrantFiled: November 8, 2019Date of Patent: December 1, 2020Assignee: Toshiba Memory CorporationInventors: Yasuhito Yoshimizu, Yoshiro Shimojo, Shinya Arai
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Publication number: 20200303395Abstract: A semiconductor storage device includes a first conductive layer, a second conductive layer, a third conductive layer, a contact plug, a memory trench extending between the second conductive layer and the third conductive layer. The memory trench is formed around the contact plug, and surrounds a first area in which the contact plug is disposed. A second area is separated from the first area and includes a pillar penetrating the first conductive layer. The second conductive layer extends between the first and second areas, and is connected to the first conductive layer. The third conductive layer is on the opposite side of the first area to the second area, and is connected to the first conductive layer.Type: ApplicationFiled: September 3, 2019Publication date: September 24, 2020Applicant: TOSHIBA MEMORY CORPORATIONInventors: Keisuke NAKATSUKA, Yoshitaka KUBOTA, Tetsuaki UTSUMI, Yoshiro SHIMOJO, Ryota KATSUMATA
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Publication number: 20200273869Abstract: According to one embodiment, a semiconductor memory device includes: a substrate; a first interconnect; a second interconnect; a plurality of third interconnects; a fourth interconnect; a semiconductor member; a charge storage member; and a conductive member. One of the plurality of third interconnects is disposed on two second-direction sides of the conductive member. Portions of the one of the plurality of third interconnects disposed on the two second-direction sides of the conductive member are formed as one body.Type: ApplicationFiled: May 14, 2020Publication date: August 27, 2020Applicant: Toshiba Memory CorporationInventor: Yoshiro Shimojo
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Patent number: 10672779Abstract: According to one embodiment, a semiconductor memory device includes: a substrate; a first interconnect; a second interconnect; a plurality of third interconnects; a fourth interconnect; a semiconductor member; a charge storage member; and a conductive member. One of the plurality of third interconnects is disposed on two second-direction sides of the conductive member. Portions of the one of the plurality of third interconnects disposed on the two second-direction sides of the conductive member are formed as one body.Type: GrantFiled: January 2, 2019Date of Patent: June 2, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventor: Yoshiro Shimojo
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Publication number: 20200075461Abstract: According to one embodiment, a stacked body includes a plurality of electrode layers stacked with an insulator interposed. A conductive via pierces the stacked body, and connects an upper layer interconnect and a lower layer interconnect. A insulating film is provided between the via and the stacked body. A distance along a diametral direction of the via between a side surface of the via and an end surface of one of the electrode layers opposing the side surface of the via is greater than a distance along the diametral direction between the side surface of the via and an end surface of the insulator opposing the side surface of the via.Type: ApplicationFiled: November 8, 2019Publication date: March 5, 2020Applicant: Toshiba Memory CorporationInventors: Yasuhito YOSHIMIZU, Yoshiro SHIMOJO, Shinya ARAI
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Publication number: 20200043942Abstract: According to one embodiment, a semiconductor memory device includes: a first interconnect layer including a first electrode that extends in a first direction and a second electrode that extends in a second direction and is in contact with one end of the first electrode; a second interconnect layer including a third electrode that is provided adjacently to the first electrode and a fourth electrode that is in contact with one end of the third electrode; a first semiconductor layer provided between the first electrode and the third electrode; a first charge storage layer provided between the first semiconductor layer and the first electrode; a second charge storage layer provided between the first semiconductor layer and the third electrode; and a first bit line provided above the first semiconductor layer and extending in the first direction.Type: ApplicationFiled: December 21, 2018Publication date: February 6, 2020Applicant: Toshiba Memory CorporationInventors: Yoshiro SHIMOJO, Tomoya Sanuki
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Patent number: 10515873Abstract: According to one embodiment, a stacked body includes a plurality of electrode layers stacked with an insulator interposed. A conductive via pierces the stacked body, and connects an upper layer interconnect and a lower layer interconnect. A insulating film is provided between the via and the stacked body. A distance along a diametral direction of the via between a side surface of the via and an end surface of one of the electrode layers opposing the side surface of the via is greater than a distance along the diametral direction between the side surface of the via and an end surface of the insulator opposing the side surface of the via.Type: GrantFiled: September 7, 2017Date of Patent: December 24, 2019Assignee: Toshiba Memory CorporationInventors: Yasuhito Yoshimizu, Yoshiro Shimojo, Shinya Arai
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Patent number: 10504918Abstract: A memory device includes a memory region, a connection region, an interconnection layer and a circuit. The memory region includes electrode layers and semiconductor layers. The electrode layers are stacked in a first direction, and the semiconductor layers extend in the first direction through the electrode layers. The connection region is surrounded with the memory region, and includes an insulating body and contact plugs. The insulating body has a thickness in the first direction thicker than a stacked width in the first direction of the electrode layers, and the contact plugs extending in the first direction through the insulating body. The interconnection layer includes interconnections electrically connected respectively to the electrode layers and some of the semiconductor layers. The electrode layers and the insulating body are positioned between the circuit and the interconnection layer in the first direction.Type: GrantFiled: July 25, 2018Date of Patent: December 10, 2019Assignee: Toshiba Memory CorporationInventors: Yoshiro Shimojo, Masahisa Sonoda
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Publication number: 20190287985Abstract: A memory device includes a memory region, a connection region, an interconnection layer and a circuit. The memory region includes electrode layers and semiconductor layers. The electrode layers are stacked in a first direction, and the semiconductor layers extend in the first direction through the electrode layers. The connection region is surrounded with the memory region, and includes an insulating body and contact plugs. The insulating body has a thickness in the first direction thicker than a stacked width in the first direction of the electrode layers, and the contact plugs extending in the first direction through the insulating body. The interconnection layer includes interconnections electrically connected respectively to the electrode layers and some of the semiconductor layers. The electrode layers and the insulating body are positioned between the circuit and the interconnection layer in the first direction.Type: ApplicationFiled: July 25, 2018Publication date: September 19, 2019Applicant: Toshiba Memory CorporationInventors: Yoshiro SHIMOJO, Masahisa Sonoda
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Publication number: 20190139972Abstract: According to one embodiment, a semiconductor memory device includes: a substrate; a first interconnect; a second interconnect; a plurality of third interconnects; a fourth interconnect; a semiconductor member; a charge storage member; and a conductive member. One of the plurality of third interconnects is disposed on two second-direction sides of the conductive member. Portions of the one of the plurality of third interconnects disposed on the two second-direction sides of the conductive member are formed as one body.Type: ApplicationFiled: January 2, 2019Publication date: May 9, 2019Applicant: TOSHIBA MEMORY CORPORATIONInventor: Yoshiro Shimojo