Abstract: A semiconductor memory device according to an embodiment includes: first and second memory columnar bodies aligned in a second direction intersecting a first direction, the first and second memory columnar bodies respectively including a semiconductor layer and extending in the first direction; a bit line disposed above the first and second memory columnar bodies; and a first connecting line disposed between the first and second memory columnar bodies and the bit line in the first direction and electrically coupled to the semiconductor layers of the first and second memory columnar bodies and the bit line, the first connecting line extending linearly in the second direction, and a center line widthwise of the first connecting line being in a position displaced in a third direction, the third direction intersecting the first and second directions, from positions of centers of the first and second memory columnar bodies.

Abstract: According to one embodiment, a semiconductor memory device includes: a substrate; a first interconnect; a second interconnect; a plurality of third interconnects; a fourth interconnect; a semiconductor member; a charge storage member; and a conductive member. One of the plurality of third interconnects is disposed on two second-direction sides of the conductive member. Portions of the one of the plurality of third interconnects disposed on the two second-direction sides of the conductive member are formed as one body.

Abstract: According to one embodiment, a stacked body includes a plurality of electrode layers stacked with an insulator interposed. A conductive via pierces the stacked body, and connects an upper layer interconnect and a lower layer interconnect. A insulating film is provided between the via and the stacked body. A distance along a diametral direction of the via between a side surface of the via and an end surface of one of the electrode layers opposing the side surface of the via is greater than a distance along the diametral direction between the side surface of the via and an end surface of the insulator opposing the side surface of the via.

Abstract: According to one embodiment, a semiconductor memory device includes: a substrate; a first interconnect; a second interconnect; a plurality of third interconnects; a fourth interconnect; a semiconductor member; a charge storage member; and a conductive member. One of the plurality of third interconnects is disposed on two second-direction sides of the conductive member. Portions of the one of the plurality of third interconnects disposed on the two second-direction sides of the conductive member are formed as one body.

Abstract: According to one embodiment, a semiconductor memory device includes: a substrate; a first interconnect; a second interconnect; a plurality of third interconnects; a fourth interconnect; a semiconductor member; a charge storage member; and a conductive member. One of the plurality of third interconnects is disposed on two second-direction sides of the conductive member. Portions of the one of the plurality of third interconnects disposed on the two second-direction sides of the conductive member are formed as one body.

Abstract: According to one embodiment, a semiconductor memory device includes a structural body, first to fourth pillars, a first interconnection, a second interconnection, a third interconnection, and a fourth interconnection. The first to fourth pillars are provided within the structural body extending along the first direction. A first distance between the first pillar and the first interconnection is greater than a second distance between the third pillar and the third interconnection. The first distance is greater than a third distance between the fourth pillar and the fourth interconnection. A fourth distance between the second pillar and the second interconnection is greater than the second distance. The fourth distance is greater than the third distance.

Abstract: According to one embodiment, a semiconductor memory device includes: a substrate; a first interconnect; a second interconnect; a plurality of third interconnects; a fourth interconnect; a semiconductor member; a charge storage member; and a conductive member. One of the plurality of third interconnects is disposed on two second-direction sides of the conductive member. Portions of the one of the plurality of third interconnects disposed on the two second-direction sides of the conductive member are formed as one body.

Abstract: A semiconductor memory device according to an embodiment includes: first and second memory columnar bodies aligned in a second direction intersecting a first direction, the first and second memory columnar bodies respectively including a semiconductor layer and extending in the first direction; a bit line disposed above the first and second memory columnar bodies; and a first connecting line disposed between the first and second memory columnar bodies and the bit line in the first direction and electrically coupled to the semiconductor layers of the first and second memory columnar bodies and the bit line, the first connecting line extending linearly in the second direction, and a center line widthwise of the first connecting line being in a position displaced in a third direction, the third direction intersecting the first and second directions, from positions of centers of the first and second memory columnar bodies.

Abstract: In general, according to one embodiment, a semiconductor memory device includes a substrate, a stacked body, a semiconductor pillar, a memory film, a partitioning member, a first interlayer insulating film, and a first plug. The stacked body is provided on the substrate, and including a plurality of electrode films and a plurality of insulating films. The semiconductor pillar is provided in the stacked body. The partitioning member is provided in the stacked body. The first plug is connected to the semiconductor pillar. A central axis of the first plug is shifted from a central axis of the semiconductor pillar so as to approach the nearest partitioning member.

Abstract: According to one embodiment, a semiconductor memory device includes a structural body, first to fourth pillars, a first interconnection, a second interconnection, a third interconnection, and a fourth interconnection. The first to fourth pillars provides within the structural body extending along the first direction. A first distance between the first pillar and the first interconnection is greater than a second distance between the third pillar and the third interconnection. The first distance is greater than a third distance between the fourth pillar and the fourth interconnection. A fourth distance between the second pillar and the second interconnection is greater than the second distance. The fourth distance is greater than the third distance.

Abstract: In general, according to one embodiment, a semiconductor memory device includes a substrate, a stacked body, a semiconductor pillar, a memory film, a partitioning member, a first interlayer insulating film, and a first plug. The stacked body is provided on the substrate, and including a plurality of electrode films and a plurality of insulating films. The semiconductor pillar is provided in the stacked body. The partitioning member is provided in the stacked body. The first plug is connected to the semiconductor pillar. A central axis of the first plug is shifted from a central axis of the semiconductor pillar so as to approach the nearest partitioning member.

Abstract: According to one embodiment, the first columnar part includes a first channel body and a first charge storage film. The second columnar part includes a second channel body and a second charge storage film. The second columnar part is provided adjacent in the first direction to the first columnar part. The connection part connects a lower end of the first channel body and a lower end of the second channel body. Each of the source layers is connected to an upper end of the first columnar part. Each of the bit lines is connected to an upper end of the second columnar part of every (n+1)-th memory string of a plurality of memory strings arranged in the first direction.

Abstract: According to one embodiment, the memory strings are disposed in a first direction and a second direction. The source layers extend in the second direction on the memory strings and are separated in the first direction. The bit lines extend in the first direction on the memory strings and are separated in the second direction. The memory string includes a first columnar section, a second columnar section, and a connecting section. The stacked body includes a plurality of blocks separated from one another in the first direction. The source layer is connected to an upper end of the first columnar section. The bit line is connected to an upper end of the second columnar section of the memory string belonging to a block selected out of the plurality of blocks.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes: a stacked body including each of a plurality of electrode layers and each of a plurality of insulating layers stacked alternately; a first interlayer insulating film; a select gate electrode; a second interlayer insulating film; a pair of semiconductor layers; a first insulating film; a second insulating film; a third interlayer insulating film; a first contact electrode connected to one upper end of the pair of semiconductor layers; a second contact electrode connected to the other upper end of the pair of semiconductor layers; a third contact electrode connected to the second contact electrode; a first interconnect layer connected to the first contact electrode; and a second interconnect layer connected to the third contact electrode.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a semiconductor layer, first and second stacked bodies, first and second channel body layers, first and second memory films. The first stacked body includes electrode layers and first insulating films alternately stacked on the semiconductor layer. The first channel body layers pierces through the first stacked body in a stacking direction. Lower ends of the first channel body layers are connected. The first memory film is provided between the first channel body layers and the electrode layers. The second channel body layers pierces through the first stacked body in the stacking direction. Lower ends of the second channel body layers are connected. The second memory film is provided between the second channel body layers and the electrode layers. The second stacked body includes a first interlayer insulating film and a select gate layer.

Abstract: According to one embodiment, a semiconductor device includes a plurality of contact electrodes that reach corresponding conductive layers. Each of the contact electrodes includes a columnar portion, a stopper, and a first connection portion. The columnar portion extends in a stacked direction of the stacked body. The stopper covers the side of the columnar portion. The first connection portion is provided at a lower edge of the columnar portion. The first connection portion is in contact with the corresponding conductive layer. A cross-section dimension of the first connection portion in a direction orthogonal to the stacked direction is larger than a cross-section of the lower edge of the columnar portion. An etching rate of a material for the stopper is lower than an etching rate of a material for the first insulating layer.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a semiconductor layer, first and second stacked bodies, first and second channel body layers, first and second memory films. The first stacked body includes electrode layers and first insulating films alternately stacked on the semiconductor layer. The first channel body layers pierces through the first stacked body in a stacking direction. Lower ends of the first channel body layers are connected. The first memory film is provided between the first channel body layers and the electrode layers. The second channel body layers pierces through the first stacked body in the stacking direction. Lower ends of the second channel body layers are connected. The second memory film is provided between the second channel body layers and the electrode layers. The second stacked body includes a first interlayer insulating film and a select gate layer.

Abstract: A semiconductor device includes: a semiconductor substrate and a transistor formed on the semiconductor substrate. The semiconductor device also includes: a first interlayer insulation film formed on the semiconductor substrate including the upper portion of the transistor, a first contact formed to be connected through the first interlayer insulation film to the transistor, a ferroelectric capacitor formed to be connected to the first contact, a second interlayer insulation film formed on the first interlayer insulation film, and a second contact formed to connect the ferroelectric capacitor to a wiring through the second interlayer insulation film. The contact surfaces between the second contact and the ferroelectric capacitor have the same planar shape.

Abstract: According to a method for manufacturing a semiconductor memory device of the present invention, a capacitor lower electrode film is left on the wiring layer located above a dummy transistor. In this manner, when processing of the capacitors is performed by removing a capacitor upper electrode film and a ferroelectric film, removal of the wiring layer can be prevented, and the connection between the diffusion layer of a select transistor and a bit line can be secured.

Abstract: A semiconductor storage device wherein a plurality of ferroelectric capacitors are sufficiently covered with a hydrogen barrier film formed thereon comprises a field effect transistor formed on one surface side of a semiconductor substrate, a plurality of ferroelectric capacitors formed close to each other above the field effect transistor, an insulting film configured to cover the plurality of ferroelectric capacitors and planarised a space between adjacent ferroelectric capacitors in a self-aligned manner during formation thereof, and a hydrogen barrier film formed on the insulating film.