Patents by Inventor You Chye How
You Chye How has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150243639Abstract: A method for packaging integrated circuit die such that each package includes die with integrated passive components mounted to either the back surface, the active surface or both the back and active surfaces of the die.Type: ApplicationFiled: February 27, 2014Publication date: August 27, 2015Applicant: Texas Instruments IncorporatedInventors: You Chye How, Siew Kee Lee, Huay Yann Tay
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Publication number: 20150108626Abstract: A multilevel leadframe for an integrated circuit package is provided that has a plurality of lead lines formed in a first level and bond pads formed in a second level. A first set of bond pads is arranged in a first row and are separated from an adjacent bond pad by a bond pad clearance distance. A second set of bond pads is arranged in second row adjacent the first row of bond pads. Each bond pad in the second row may be connected to one of the plurality of lead lines on the first level that is routed between adjacent bond pads in the first row. Since the bond pads in the first row are on a different level then the lead lines, the bond pads may be spaced close together.Type: ApplicationFiled: December 23, 2014Publication date: April 23, 2015Inventors: Lee Han Meng@ Eugene Lee, You Chye How
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Publication number: 20150054145Abstract: An integrated circuit package having a die attach paddle, a power die mounted on the die attach paddle and a controller die mounted on the die attach paddle. The die attach paddle has at least one recessed portion at least partially underlying the controller die.Type: ApplicationFiled: August 23, 2013Publication date: February 26, 2015Applicant: Texas Instruments IncorporatedInventors: You Chye How, Maria Christina Bernardo Violante
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Publication number: 20150053586Abstract: A carrier tape for transporting electronic components having a linearly displaceable continuous web and a plurality of pocket structures connected to the continuous web. The pocket structures are adapted to receive the electronic components. Each of the plurality of pocket structures defines an opening to enable passage of the electronic component into the pocket structure. Each of the pocket structures define at least one tab that is adapted to retain an electronic component in the pocket structure without a closure member.Type: ApplicationFiled: August 22, 2013Publication date: February 26, 2015Applicant: Texas Instruments IncorporatedInventors: You Chye How, Siew Kee Lee, Huay Yann Tay
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Publication number: 20150035130Abstract: A packaged semiconductor device has a semiconductor substrate with circuitry formed thereon. A shield plate is mounted over a designated region of the substrate and separated from the semiconductor substrate by a separator, such that the shield plate is separated from the designated region of the substrate by a distance. Mold compound encapsulates the semiconductor substrate and the shield plate, but is prevented from touching the designated region of the substrate by the shield plate.Type: ApplicationFiled: July 30, 2013Publication date: February 5, 2015Applicant: Texas Instruments IncorporatedInventor: You Chye How
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Publication number: 20140346656Abstract: A multilevel leadframe for an integrated circuit package is provided that has a plurality of lead lines formed in a first level and bond pads formed in a second level. A first set of bond pads is arranged in a first row and are separated from an adjacent bond pad by a bond pad clearance distance. A second set of bond pads is arranged in second row adjacent the first row of bond pads. Each bond pad in the second row may be connected to one of the plurality of lead lines on the first level that is routed between adjacent bond pads in the first row. Since the bond pads in the first row are on a different level then the lead lines, the bond pads may be spaced close together.Type: ApplicationFiled: May 27, 2013Publication date: November 27, 2014Inventors: Lee Han Meng@ Eugene Lee, You Chye How
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Patent number: 8647966Abstract: In one aspect of the present invention, a method of sawing a semiconductor wafer will be described. A semiconductor wafer is positioned in a wafer sawing apparatus that includes a sawing blade and a movable support structure that physically supports the semiconductor wafer. The semiconductor wafer is coupled with the support structure with various layers, including a die attach film, an adhesive and a base film. The die attach film is cut with the sawing blade. During the cutting operation, a contact portion of the sawing blade engages one of the layers and moves at least partly in one direction. While the contact portion of the sawing blade engages the layer, the support structure moves in the opposite direction. Various aspects of the present invention relate to arrangements and a wafer sawing apparatus that involve the aforementioned sawing method.Type: GrantFiled: June 9, 2011Date of Patent: February 11, 2014Assignee: National Semiconductor CorporationInventors: Ken Fei Lim, You Chye How, Kooi Choon Ooi
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Publication number: 20120313231Abstract: In one aspect of the present invention, a method of sawing a semiconductor wafer will be described. A semiconductor wafer is positioned in a wafer sawing apparatus that includes a sawing blade and a movable support structure that physically supports the semiconductor wafer. The semiconductor wafer is coupled with the support structure with various layers, including a die attach film, an adhesive and a base film. The die attach film is cut with the sawing blade. During the cutting operation, a contact portion of the sawing blade engages one of the layers and moves at least partly in one direction. While the contact portion of the sawing blade engages the layer, the support structure moves in the opposite direction. Various aspects of the present invention relate to arrangements and a wafer sawing apparatus that involve the aforementioned sawing method.Type: ApplicationFiled: June 9, 2011Publication date: December 13, 2012Applicant: NATIONAL SEMICONDUCTOR CORPORATIONInventors: Ken Fei LIM, You Chye HOW, Kooi Choon OOI
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Patent number: 8048781Abstract: Methods of packaging integrated circuits are described. One method relates to attaching a singulated device wafer to a substrate. The singulated device wafer includes a multiplicity of integrated circuit dice arranged in a first configuration. The method also involves a substrate, which includes a sacrificial semiconductor wafer having device areas with metalized contacts. The device areas on the substrate may be arranged in a configuration matching that of the dice on the device wafer. The method also entails aligning the singulated device wafer as a whole with the substrate so that the dice of the device wafer are positioned substantially simultaneously over associated device areas on the substrate. The method also involves attaching the dice from the singulated wafer as a whole substantially simultaneously to the substrate such that each die of the device wafer is attached to an associated device area of the substrate.Type: GrantFiled: January 24, 2008Date of Patent: November 1, 2011Assignee: National Semiconductor CorporationInventor: You Chye How
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Patent number: 8030138Abstract: Panel level methods and systems for packaging integrated circuits are described. In a method aspect of the invention, a substrate formed from a sacrificial semiconductor wafer is provided having a plurality of metallized device areas patterned thereon. Each device area includes an array of metallized contacts and a die attach area. Dice are mounted onto each device area and electrically connected to the array of contacts. The entire surface of the substrate including the dice, contacts and electrical connections is then encapsulated. The semiconductor wafer is then sacrificed leaving portions of the contacts exposed allowing the contacts to be used as external contacts in an IC package. In various embodiments, other structures, including die attach pads, may be incorporated into the device areas as desired. By way of example, structures having thicknesses in the range of 10 to 20 microns are readily attainable.Type: GrantFiled: July 10, 2006Date of Patent: October 4, 2011Assignee: National Semiconductor CorporationInventors: You Chye How, Shee Min Yeong, Peng Soon Lim, Sek Hoi Chong
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Patent number: 8018050Abstract: An IC package and methods for making the same are described. The IC package includes a die and a heat sink that is attached to the back surface of the die with a thermal interface material layer. The heat sink includes a base and a partition. The partition extends around the periphery of the base and is offset from the outer edge of the base such that a ledge region is formed that surrounds the periphery of the base. The inner surfaces of the partition define an inner region that includes heat dissipation structures. A molding material encapsulates at least portions of the die and the ledge region around the periphery of the heat sink while leaving the inner region of the heat sink unencapsulated by molding material and exposed. The molding material covering the ledge region provides a locking feature that secures the heat sink in the package.Type: GrantFiled: November 1, 2007Date of Patent: September 13, 2011Assignee: National Semiconductor CorporationInventors: You Chye How, Shee Min Yeong
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Patent number: 7868433Abstract: The present invention relates to methods and arrangements for forming a low stress cavity package. Particular methods may be performed with existing packaging equipment. In one such method, a leadframe laminated with adhesive film is provided. Integrated circuit dice are connected to the leadframe by reflowing solder between bond pads on the active surface of each die and the leadframe. A viscous thermosetting material is dispensed around the periphery of the active surface of each die. The thermosetting material fills gaps between the solder joint connections and the adhesive film. As a result, the thermosetting material, solder joint connections, each integrated circuit die and the adhesive film define and seal a protective cavity between the active surface of the die and the adhesive film. Portions of each die, leads, solder joint connections and adhesive film are encapsulated with a molding material that is prevented from entering the sealed cavity.Type: GrantFiled: August 29, 2008Date of Patent: January 11, 2011Assignee: National Semiconductor CorporationInventors: Peng Soon Lim, Shee Min Yeong, You Chye How
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Patent number: 7863757Abstract: Panel level methods and systems for packaging integrated circuits are described. In a method aspect of the invention, a substrate formed from a sacrificial semiconductor wafer is provided having a plurality of metallized device areas patterned thereon. Each device area includes an array of metallized contacts. Dice are mounted onto each device area and electrically connected to the array of contacts. The surface of the substrate including the dice, contacts and electrical connections is then encapsulated. The semiconductor wafer is then sacrificed leaving portions of the contacts exposed allowing the contacts to be used as external contacts in an IC package. In various embodiments, other structures, including saw street structures, may be incorporated into the device areas as desired. By way of example, structures having thicknesses in the range of 10 to 20 microns are readily attainable.Type: GrantFiled: May 27, 2010Date of Patent: January 4, 2011Assignee: National Semiconductor CorporationInventors: You Chye How, Shee Min Yeong
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Publication number: 20100237487Abstract: Panel level methods and systems for packaging integrated circuits are described. In a method aspect of the invention, a substrate formed from a sacrificial semiconductor wafer is provided having a plurality of metallized device areas patterned thereon. Each device area includes an array of metallized contacts. Dice are mounted onto each device area and electrically connected to the array of contacts. The surface of the substrate including the dice, contacts and electrical connections is then encapsulated. The semiconductor wafer is then sacrificed leaving portions of the contacts exposed allowing the contacts to be used as external contacts in an IC package. In various embodiments, other structures, including saw street structures, may be incorporated into the device areas as desired. By way of example, structures having thicknesses in the range of 10 to 20 microns are readily attainable.Type: ApplicationFiled: May 27, 2010Publication date: September 23, 2010Applicant: NATIONAL SEMICONDUCTOR CORPORATIONInventors: You Chye How, Shee Min Yeong
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Patent number: 7749809Abstract: Panel level methods and systems for packaging integrated circuits are described. In a method aspect of the invention, a substrate formed from a sacrificial semiconductor wafer is provided having a plurality of metallized device areas patterned thereon. Each device area includes an array of metallized contacts. Dice are mounted onto each device area and electrically connected to the array of contacts. The surface of the substrate including the dice, contacts and electrical connections is then encapsulated. The semiconductor wafer is then sacrificed leaving portions of the contacts exposed allowing the contacts to be used as external contacts in an IC package. In various embodiments, other structures, including saw street structures, may be incorporated into the device areas as desired. By way of example, structures having thicknesses in the range of 10 to 20 microns are readily attainable.Type: GrantFiled: December 17, 2007Date of Patent: July 6, 2010Assignee: National Semiconductor CorporationInventors: You Chye How, Shee Min Yeong
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Publication number: 20100052123Abstract: The present invention relates to methods and arrangements for forming a low stress cavity package. Particular methods may be performed with existing packaging equipment. In one such method, a leadframe laminated with adhesive film is provided. Integrated circuit dice are connected to the leadframe by reflowing solder between bond pads on the active surface of each die and the leadframe. A viscous thermosetting material is dispensed around the periphery of the active surface of each die. The thermosetting material fills gaps between the solder joint connections and the adhesive film. As a result, the thermosetting material, solder joint connections, each integrated circuit die and the adhesive film define and seal a protective cavity between the active surface of the die and the adhesive film. Portions of each die, leads, solder joint connections and adhesive film are encapsulated with a molding material that is prevented from entering the sealed cavity.Type: ApplicationFiled: August 29, 2008Publication date: March 4, 2010Applicant: NATIONAL SEMICONDUCTOR CORPORATIONInventors: Peng Soon LIM, Shee Min YEONG, You Chye HOW
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Patent number: 7582954Abstract: Apparatuses and methods directed to a semiconductor chip package having an optical component are disclosed. Packages include a die having a light sensing region and a stress buffer on a first surface, a first opaque encapsulant having an opening therethrough disposed atop the first surface, and a second transparent or translucent encapsulant formed within the first encapsulant opening and directly atop and contacting the light sensing region. A leadless leadframe or other conductive component can be coupled to a second surface of the die. The die may also have light sensitive regions that are shielded by the first encapsulant and/or stress buffer. The stress buffer can be a layer formed at the wafer stage or a dam formed at the panel stage. A customized mold is used while dispensing the first encapsulant such that the opening therethrough is properly formed.Type: GrantFiled: February 25, 2008Date of Patent: September 1, 2009Assignee: National Semiconductor CorporationInventors: Peng Soon Lim, Terh Kuen Yii, You Chye How, Sek Hoi Chong, Shee Min Yeong
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Publication number: 20090212382Abstract: Apparatuses and methods directed to a semiconductor chip package having an optical component are disclosed. Packages include a die having a light sensing region and a stress buffer on a first surface, a first opaque encapsulant having an opening therethrough disposed atop the first surface, and a second transparent or translucent encapsulant formed within the first encapsulant opening and directly atop and contacting the light sensing region. A leadless leadframe or other conductive component can be coupled to a second surface of the die. The die may also have light sensitive regions that are shielded by the first encapsulant and/or stress buffer. The stress buffer can be a layer formed at the wafer stage or a dam formed at the panel stage. A customized mold is used while dispensing the first encapsulant such that the opening therethrough is properly formed.Type: ApplicationFiled: February 25, 2008Publication date: August 27, 2009Applicant: NATIONAL SEMICONDUCTOR CORPORATIONInventors: Peng Soon LIM, Terh Kuen YII, You Chye HOW, Sek Hoi CHONG, Shee Min YEONG
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Publication number: 20090189279Abstract: Methods of packaging integrated circuits are described. One method relates to attaching a singulated device wafer to a substrate. The singulated device wafer includes a multiplicity of integrated circuit dice arranged in a first configuration. The method also involves a substrate, which includes a sacrificial semiconductor wafer having device areas with metalized contacts. The device areas on the substrate may be arranged in a configuration matching that of the dice on the device wafer. The method also entails aligning the singulated device wafer as a whole with the substrate so that the dice of the device wafer are positioned substantially simultaneously over associated device areas on the substrate. The method also involves attaching the dice from the singulated wafer as a whole substantially simultaneously to the substrate such that each die of the device wafer is attached to an associated device area of the substrate.Type: ApplicationFiled: January 24, 2008Publication date: July 30, 2009Applicant: NATIONAL SEMICONDUCTOR CORPORATIONInventor: You Chye HOW
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Publication number: 20090152707Abstract: Panel level methods and systems for packaging integrated circuits are described. In a method aspect of the invention, a substrate formed from a sacrificial semiconductor wafer is provided having a plurality of metallized device areas patterned thereon. Each device area includes an array of metallized contacts. Dice are mounted onto each device area and electrically connected to the array of contacts. The surface of the substrate including the dice, contacts and electrical connections is then encapsulated. The semiconductor wafer is then sacrificed leaving portions of the contacts exposed allowing the contacts to be used as external contacts in an IC package. In various embodiments, other structures, including saw street structures, may be incorporated into the device areas as desired. By way of example, structures having thicknesses in the range of 10 to 20 microns are readily attainable.Type: ApplicationFiled: December 17, 2007Publication date: June 18, 2009Applicant: NATIONAL SEMICONDUCTOR CORPORATIONInventors: You Chye HOW, Shee Min YEONG