Patents by Inventor You Chye How

You Chye How has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090115037
    Abstract: An IC package and methods for making the same are described. The IC package includes a die and a heat sink that is attached to the back surface of the die with a thermal interface material layer. The heat sink includes a base and a partition. The partition extends around the periphery of the base and is offset from the outer edge of the base such that a ledge region is formed that surrounds the periphery of the base. The inner surfaces of the partition define an inner region that includes heat dissipation structures. A molding material encapsulates at least portions of the die and the ledge region around the periphery of the heat sink while leaving the inner region of the heat sink unencapsulated by molding material and exposed. The molding material covering the ledge region provides a locking feature that secures the heat sink in the package.
    Type: Application
    Filed: November 1, 2007
    Publication date: May 7, 2009
    Applicant: NATIONAL SEMICONDUCTOR CORPORATION
    Inventors: You Chye HOW, Shee Min YEONG
  • Publication number: 20080242003
    Abstract: A method for forming integral heat sinks on back surfaces of integrated circuit devices at wafer level is described. A first metallic layer is deposited over the back surface of a wafer. A second metallic layer is deposited over the first metallic layer. Optionally, a third metallic layer is deposited over the second metallic layer. The first metallic layer, the second metallic layer, and optionally the third metallic layer form the integral heat sink for the wafer. When the wafer is diced into multiple semiconductor devices, each semiconductor device has an integral heat sink formed on its back surface that includes the first metallic layer, the second metallic layer, and optionally the third metallic layer. Optionally, each semiconductor device is connected to a lead frame via solder bumps or bonding wires to form an integrated circuit (IC) package.
    Type: Application
    Filed: March 26, 2007
    Publication date: October 2, 2008
    Applicant: NATIONAL SEMICONDUCTOR CORPORATION
    Inventors: You Chye HOW, Shee Min YEONG, Seong Mun CHAN, Wee Khim TENG
  • Patent number: 6972244
    Abstract: Wafer level techniques for marking the back surfaces of integrated circuit devices are described. The back surface of the wafer is laser marked while being supported by a mount tape. In some embodiments, the mount tape is sufficiently transparent that the laser light passes through the mount tape and marks the back surface of the wafer. In other embodiments, the laser may actually burn the mounting tape (or portions thereof) during the marking process. The marking may be done on any suitable back surface material including polymeric backcoatings, metalized films or directly on semiconductor materials.
    Type: Grant
    Filed: April 23, 2004
    Date of Patent: December 6, 2005
    Assignee: National Semiconductor Corporation
    Inventors: Viraj A. Patwardhan, Nikhil Vishwanath Kelkar, You Chye How, Tian Oon Goh, Soi Chong Low