Abstract: A printed circuit board, a method of manufacturing a printed circuit board, and an electronic component module including a printed circuit board are provided. The printed circuit board includes a circuit board having a cavity, and a connection board including metal patterns, the connection board disposed in the cavity with the metal patterns disposed substantially vertically in the circuit board.

Abstract: There are provided a printed circuit board, an electronic component module and a method of manufacturing the same. The printed circuit board includes a circuit board including a through hole and a first circuit pattern, and a connection board having a microcircuit structure including a second circuit pattern, the connection board accommodated in the through hole.

Abstract: A printed circuit board includes an insulating layer; and a circuit pattern formed on the insulating layer. The circuit pattern includes a seed layer and a metal layer formed on the seed layer, and both sides of the seed layer are formed with an etched groove. Also, a method of manufacturing a printed circuit board includes: forming a seed layer on the insulating layer; forming a plating resist formed with an opening on the seed layer; forming a circuit pattern by performing plating processing on the opening; removing the plating resist; forming a passivation layer on the circuit pattern; performing dry etching on a remaining portion other than a side wall of the passivation layer; and performing wet etching the seed layer exposed on a surface by the dry etching.

Abstract: A circuit board, and a package substrate and an electronic device that includes a circuit board are disclosed. The circuit board includes a core layer, a base pattern layer disposed on the core layer and a through-hole conductor that goes through the core layer, the base pattern layer including a circuit pattern that includes a conductive pad on the through-hole conductor, an insulator layer including at least one insulating layer stacked on the core layer and the base pattern layer, and a laminated pattern layer including a plurality of vias and a laminated circuit pattern, the plurality of vias penetrating the insulating layer, and the laminated circuit pattern being disposed on the insulating layer and including a plurality of via pads formed on the vias respectively.

Abstract: There are provided a chip embedded board and a method of manufacturing the same. The chip embedded board includes: a core substrate; a first build-up layer formed on one surface of the core substrate and having a cavity formed therein; a chip disposed in the cavity; and an insulating layer filled in the cavity in which the chip is disposed, wherein one surface of the chip is positioned in a circuit layer positioned at the outermost layer of the first build-up layer.

Abstract: A common mode filter a manufacturing method thereof are disclosed. The common mode filter in accordance with an embodiment of the present invention includes: a magnetic substrate; a receiving groove formed on the magnetic substrate; a dielectric layer formed in the receiving groove and having a coil pattern included therein; and a magnetic layer formed on upper surfaces of the dielectric layer and the magnetic substrate.

Abstract: A method for forming metallurgical interconnections and polymer adhesion of a flip chip to a substrate includes providing a chip having a set of bumps formed on a bump side thereof and a substrate having a set of interconnect points on a metallization thereon, providing a measured quantity of a polymer adhesive in a middle region of the chip on the bump side, aligning the chip with the substrate so that the set of bumps aligns with the set of interconnect points, pressing the chip and the substrate toward one another so that a portion of the polymer adhesive contacts the substrate and the bumps contact the interconnect points, and heating the bumps to a temperature sufficiently high to form a metallurgical connection between the bumps and the interconnect points.

Abstract: Microelectronic devices and method of forming a plurality of microelectronic devices on a semiconductor workpiece are disclosed herein. One such method includes placing a plurality of first interconnect elements on a side of a semiconductor workpiece, forming a layer on the side of the workpiece, reshaping the first interconnect elements by heating the first interconnect elements, and coupling a first portion of a plurality of individual second interconnect elements to corresponding first interconnect elements with a second portion of the individual second interconnect elements exposed.

Abstract: The present invention relates to a via structure having an open stub and a printed circuit board having the same. In accordance with an embodiment of the present invention, a via structure having an open stub including: a signal transmission via passing through an insulating layer; upper and lower via pads for connecting first and second transmission lines, which are respectively formed on and under the insulating layer, and the signal transmission via; and at least one open stub connected to an outer periphery of each via pad to have a shunt capacitance with each ground pattern formed on and under the insulating layer is provided. Further, a printed circuit board with a via having an open stub is provided.

Abstract: Microelectronic devices and method of forming a plurality of microelectronic devices on a semiconductor workpiece are disclosed herein. One such method includes placing a plurality of first interconnect elements on a side of a semiconductor workpiece, forming a layer on the side of the workpiece, reshaping the first interconnect elements by heating the first interconnect elements, and coupling a first portion of a plurality of individual second interconnect elements to corresponding first interconnect elements with a second portion of the individual second interconnect elements exposed.

Abstract: Disclosed herein are a thin-type common mode filter and a manufacturing method thereof. According to an exemplary embodiment of the present invention, a thin-type common mode filter includes: a ferrite substrate having an upper surface on which irregular surface roughness is formed; an insulating layer formed on the upper surface of the ferrite substrate; and a conductive coil pattern formed in the insulating layer to be spaced apart from the upper surface of the ferrite substrate. Further, a manufacturing method of a thin-type common mode filter is proposed.

Abstract: An electronic component embedded substrate is disclosed. The electronic component embedded substrate in accordance with an embodiment of the present invention includes: a core substrate having a cavity formed therein; a plurality of electronic components embedded in the cavity and arranged in a predetermined format; and a plurality of dielectric spacers interposed in between the plurality of electronic components that are adjacent to one another in the cavity.

Abstract: A common mode filter is disclosed. The common mode filter in accordance with an embodiment of the present invention includes: a magnetic substrate; a coil pattern formed on the magnetic substrate; a dielectric layer formed on the magnetic substrate so as to cover an upper part, a lower part and a side surface of the coil pattern; and a first coupling agent interposed between the magnetic substrate and the dielectric layer so as to prevent the magnetic substrate and the dielectric layer from being separated.

Abstract: Disclosed herein is an optical module including: an optical element mounted on a substrate; and an optical connector mounted corresponding to the optical element so as to change a path of an optical signal of the optical element and transfer the optical signal having the changed path. The optical module may provide various communication performances using an optical connector in which first and second connector parts are optically coupled stably to each other. Particularly, the optical module does not have a silicon optical bench (SiOB) as a medium, thereby making it possible to reduce a thickness of a product.

Abstract: Disclosed herein are a coil component and a manufacturing method thereof. The coil component includes: an electrode body including coil electrodes disposed therein, the coil electrodes having an insulating film deposited on a surface thereof; and external terminals formed at both side portions of the electrode body and connected to the coil electrodes, wherein the electrode body is made of an insulating material with which magnetic powders are mixed, in order to improve impedance characteristics.

Abstract: A common mode filter is disclosed. The common mode filter in accordance with an embodiment of the present invention includes: a magnetic substrate; a dielectric layer laminated on the magnetic substrate; an external electrode formed on the dielectric layer in such a way that one surface thereof is exposed to an outside; a conductive pattern formed on a surface of the dielectric layer so as to be located on a same plane as the external electrode and having one end thereof connected with the external electrode; an insulator film formed on a surface of the conductive pattern; and a magnetic layer formed on the insulator film so as to cover an upper surface and a lateral surface of the conductive pattern.

Abstract: Disclosed herein is a common mode filter including an internal electrode manufactured in a coil electrode form and provided with a simultaneous coil pattern in which two coil electrodes are overlapped with each other in a single layer in a direction in which a coil is wound, wherein a height of a second insulating layer formed on the internal electrode is higher than an interval between the coils. Therefore, a portion at which a parasitic capacitance is generated may be basically blocked, and a self resonant frequency (SRF) may be increased while filtering performance as the common mode filter is maintained.

Abstract: A semiconductor package and a method of manufacturing the semiconductor package are disclosed. A semiconductor package in accordance with an embodiment of the present invention includes a substrate, which is formed with a ground circuit and mounted with a semiconductor chip on one surface, a conductive ground layer, which is formed on the other surface of the substrate and connected with the ground circuit, a molding, which seals up the ground layer and the substrate having the semiconductor chip mounted thereon, and a conductive shield, which covers the molding and is connected with the ground layer. With a semiconductor package in accordance with an embodiment of the present invention, grounding for shielding is possible even in an entirely molded structure, and a double shielding structure to improve the shielding property.

Abstract: Disclosed herein are an asymmetrical multilayer substrate, an RF module, and a method for manufacturing the asymmetrical multilayer substrate. The asymmetrical multilayer substrate includes a core layer, a first pattern layer formed on one side of the core layer and including a first signal line pattern, a second pattern layer formed on the other side and including a second metal plate and a second routing line pattern, a first insulating layer thinner than the core layer formed on the second pattern layer and including a first via, and a third pattern layer formed on the first insulating layer and including a third signal line pattern, wherein an impedance transformation circuit including an impedance load and a parasitic capacitance load on the transmission line is formed for impedance matching in signal transmission between the signal line patterns formed in the upper and lower side directions of the core layer.

Abstract: A method for manufacturing an interposer includes forming a via hole in an insulation plate including a resin or a ceramic; simultaneously forming resists for a first upper redistribution layer on the top surface of the insulation plate, and a resistor for a lower redistribution layer on the bottom surface of the insulation plate; plating copper to fill the via hole and simultaneously forming the first upper redistribution layer and the lower redistribution layer along a designed circuit pattern; and forming a first upper protection layer and a lower protection layer to expose a portion of the first upper redistribution layer and a portion of the lower redistribution layer.