Abstract: An integrated circuit comprises a substrate having circuitry integrated with the substrate. Switching circuitry is selectably operable to configure signal paths to alternative mirrored pads over the substrate. At least one of the first and second signal paths may comprise a buffer in series between the switching circuit and its respective pad.

Abstract: Integrated circuit voltage generating circuits include an integrated circuit substrate, a first voltage generating circuit in the integrated substrate that is configured to generate a first voltage from a power supply voltage, and a second voltage generating circuit in the integrated circuit substrate that is configured to generate a second voltage that is different from the first voltage from the power supply voltage. A shared capacitor in the integrated circuit substrate is connected to both the first voltage generating circuit and to the second voltage generating circuit. The shared capacitor is used by the first voltage generating circuit and the second voltage generating circuit, to generate the first and second voltages.

Abstract: Devices, circuits and methods for dual voltage generation using a single charge pump. The dual voltages can be the same or different, as they are for two different components of a device. An oscillator generates an oscillating signal, and a charge pump generates a pumping voltage at a pumping node responsive to the oscillating signal. A first switching circuit is coupled to the pumping node, and outputs from the pumping voltage a first voltage to the first component. A second switching circuit is coupled to the pumping node, and outputs from the pumping voltage a second voltage to the second component. The first and second output voltages may optionally be sensed. The oscillator may be triggered and the first and second switching circuits may be controlled as needed to maintain the sensed first and second voltages at desired values and/or ranges.

Abstract: A delay line receives an input clock signal and includes a cascaded plurality of unit delay circuits. A mode register set stores a value indicative of a column-address-strobe (CAS) latency of the memory device, and an adjustment circuit varies a delay time of the unit delay circuits according to the CAS latency stored in the mode register set. A phase detector detects a phase difference between the input clock signal and an output clock signal of the delay line, and a control circuit which controls an enabled state of the unit delay circuits according to an output of said phase detector.

Abstract: Devices, circuits and methods synchronize the inputting and outputting of groups of data into a memory cell array and out of a device. Synchronizing is performed by internal clock signals, both of which are derived from a single delay feedback loop.

Abstract: Devices, circuits and methods synchronize the inputting and outputting of groups of data into a memory cell array and out of a device. Synchronizing is performed by internal clock signals, both of which are derived from a single delay feedback loop.

Abstract: An integrated circuit comprises a substrate having circuitry integrated with the substrate. Switching circuitry is selectably operable to configure signal paths to alternative mirrored pads over the substrate. At least one of the first and second signal paths may comprise a buffer in series between the switching circuit and its respective pad.

Abstract: A delay line receives an input clock signal and includes a cascaded plurality of unit delay circuits. A mode register set stores a value indicative of a column-address-strobe (CAS) latency of the memory device, and an adjustment circuit varies a delay time of the unit delay circuits according to the CAS latency stored in the mode register set. A phase detector detects a phase difference between the input clock signal and an output clock signal of the delay line, and a control circuit which controls an enabled state of the unit delay circuits according to an output of said phase detector.

Abstract: Integrated circuit voltage generating circuits include an integrated circuit substrate, a first voltage generating circuit in the integrated substrate that is configured to generate a first voltage from a power supply voltage, and a second voltage generating circuit in the integrated circuit substrate that is configured to generate a second voltage that is different from the first voltage from the power supply voltage. A shared capacitor in the integrated circuit substrate is connected to both the first voltage generating circuit and to the second voltage generating circuit. The shared capacitor is used by the first voltage generating circuit and the second voltage generating circuit, to generate the first and second voltages.

Abstract: Devices, circuits and methods for dual voltage generation using a single charge pump. The dual voltages can be the same or different, as they are for two different components of a device. An oscillator generates an oscillating signal, and a charge pump generates a pumping voltage at a pumping node responsive to the oscillating signal. A first switching circuit is coupled to the pumping node, and outputs from the pumping voltage a first voltage to the first component. A second switching circuit is coupled to the pumping node, and outputs from the pumping voltage a second voltage to the second component. The first and second output voltages may optionally be sensed. The oscillator may be triggered and the first and second switching circuits may be controlled as needed to maintain the sensed first and second voltages at desired values and/or ranges.

Abstract: An improved self burn-in circuit for a semiconductor memory generates a control signal, an address, and a test data for a burn-in test operation when a certain self burn-in test condition is satisfied. The burn-in circuit includes a burn-in detector for generating a control signal, an address signal, and a test data for a burn-in test operation when a self burn-in test condition is achieved. A memory array performs a burn-in test operation when the test data is written into and/or read from a memory cell which is selected by the address signal in accordance with the control signal.

Abstract: The present invention relates to a charge pump circuit which can vary an oscillation frequency for charge pumping in proportion to a charge consumption amount. The charge pump circuit includes: a voltage divider dividing a boosting voltage to a predetermined level; a voltage level sensing unit sensing a voltage difference between a divided voltage outputted from the voltage divider and a reference voltage, and outputting a control voltage corresponding to the sensed voltage difference; an oscillator circuit varying an oscillation frequency in accordance with the control voltage outputted from the voltage level sensing unit; and a charge pump performing a pumping operation in accordance with the output from the oscillator circuit, and outputting a boosting voltage.

Abstract: A clock synchronizing circuit provides reduced power consumption. A first phase comparator compares an external clock signal delayed for a predertermined time with a feedback clock signal to detect their phase error, and a second phase comparator compares an external clock signal with a feedback clock signal delayed for a predetermined time to detect their phase error. A charge pump changes a charge amount depending on phase error detecting signals from the first and second phase error comparators, and a phase compensator compensates the phase of the external clock signal depending on the charge amount from the charge pump. A controller controls the overall system or some portion thereof to be converted to a power save mode if the phase of the external clock signal is synchronized with that of the feedback clock signal by the phase compensator.

Abstract: A charge pump circuit of a semiconductor memory device provides high efficiency. A high voltage detector outputs a high voltage detection signal. A regulator outputs a high level and a controller is triggered at a descent edge of a row access strobe bar signal and outputs a high level row access strobe bar pulse signal. An oscillator generates an oscillation pulse signal in accordance with the high level turn-on signal outputted from the regulator. A charge pump performs a pumping operation until the oscillation pulse signal reaches a potential of (Vdd−2Vt) when the oscillation pulse signal is applied thereto, and halts the pumping operation when the high level high voltage detection signal is applied. A pull-up transistor precharges the raised voltage Vpp to a potential of (Vdd−Vt) when power is turned on.

Abstract: A negative delay circuit (NDC) has an NDC array operated in a high frequency. The circuit varies a number of unit delay stages at an input stage of the NDC array according to a locking fail signal in a low frequency region. The NDC can carry out a negative delay operation in a wide band even when a number of the stages in the NDC array is small. The present invention decreases a size of a chip, and in addition, reduces an unnecessary current consumption by preventing a locking from re-occurring at a stage in a back portion because the NDC array has a delay value less than one clock.

Abstract: Disclose is a semiconductor memory device including a plurality of memory cell arrays, row and column decoders for selecting/driving each memory cell, and a plurality of bit line sensing amplifier arrays for sensing data of each memory cell, the semiconductor memory device comprising: a plurality of sub word line driver sections for driving each memory cell with a sub word line enable selection signal (SWLE) decoded by LSB address and with a global word line signal (GWLb) decoded by MSB address in the row decoder; a row decoding precharge signal generating section (RDPRi/VBFi) for applying a precharge signal to the row decoder and a voltage Vbb to the GWLb signal by means of the MSB address PXb; a level shifting section for shifting and transmitting an output signal from the column decoder to column selection lines which connects the column decoder with the bit line sensing amplifier array in series; and a data input/output controlling section for selectively applying an active signal to the bit line sensing

Abstract: Device for delaying a clock signal using a ring delay is disclosed. The device can include a delay for delaying an external clock signal eCLK as much as time delays d1+d2 of a time delay d1 occurring on reception and a time delay d2 occurring on driving an output buffer, a pulse generator for receiving the clock signal from the delay and generating rectangular pulses synchronous to rising edges, and a ring delay having a plurality of unit delays connected in a ring form for delaying and circulating the pulse signal generated in the pulse generator as well as latching a signal from each unit delay synchronous to the clock signal rCLK received in the chip. The first clock signal delay is for delaying the clock signal rCLK in a course corresponding to a number of circulation, and a second clock signal delay is for making a fine delay of the clock signal from the first clock signal delay in response to a latch signal from the ring delay.

Abstract: A clock synchronizing circuit provides reduced power consumption. A first phase comparator compares an external clock signal delayed for a predetermined time with a feedback clock signal to detect their phase error, and a second phase comparator compares an external clock signal with a feedback clock signal delayed for a predetermined time to detect their phase error. A charge pump changes a charge amount depending on phase error detecting signals from the first and second phase error comparators, and a phase compensator compensates the phase of the external clock signal depending on the charge amount from the charge pump. A controller controls the overall system or some portion thereof to be converted to a power save mode if the phase of the external clock signal is synchronized with that of the feedback clock signal by the phase compensator.

Abstract: A bit line sense amplifier overdriving method includes a step for reaching a bit line data signal to a full swing level by driving the sense amplifiers in accordance with an overdriving voltage in an overdriving pulse interval, when an overdriving pulse signal is generated at points in which the sense amplifiers are enabled and disabled in a data read operation and a data write operation. The method maintains a sufficiently long refresh interval during a refresh operation.

Abstract: A voltage pump circuit for precharging/pumping a charge to/from a pumping capacitor separately employs a voltage generator for independently supplying a well-bias voltage to a PMOS transfer transistor which transfers a charge of a precharged capacitor to produce reference voltage. The voltage of the voltage generator is applied to a well of the PMOS transfer transistor to body bias the PMOS transfer transistor and, thus, ruggedize its threshold voltage transistor. Here, the well-bias voltage equals or exceeds the reference voltage while being approximately twice a power source voltage.